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[volatile_load] add qd.volatile_load primitive (closes #648)#702

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hp/volatile-load
May 18, 2026
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[volatile_load] add qd.volatile_load primitive (closes #648)#702
hughperkins merged 5 commits into
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hp/volatile-load

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Summary

Adds qd.volatile_load(target), a top-level frontend primitive (alongside qd.atomic_*) that maps to a GlobalLoadStmt carrying a new is_volatile flag. Required for spin-wait correctness: without it, a loop like

while flags[prev] == STATE_INVALID:
    pass

is undefined at the LLVM-IR / SPIR-V level (the optimiser may hoist the load and turn the spin into an infinite loop). The portable workarounds (grid.mem_fence() inside the loop, atomic_add(flags, 0)) are correct but pay an order-of-magnitude perf tax over a real volatile read.

Closes #648.

Codegen, all four backends

  • CUDA / AMDGPU -- LLVM LoadInst::setVolatile(true), lowering to ld.volatile.global (PTX) / unhoistable global_load_* (AMDGPU). CUDA additionally suppresses the __ldg / !invariant.load read-only-cache fast path for volatile loads (the two are contradictory).
  • Vulkan / Metal -- SPIR-V OpLoad with the Volatile MemoryAccess mask via a new IRBuilder::load_variable_volatile helper. Per-load opt-in on top of the existing Metal-global use_volatile_buffer_access_ flag.

Transforms guarded

  • cache_loop_invariant_global_vars -- skip volatile loads (would hoist).
  • simplify -- skip the redundant-load search for volatile loads (the cell may have been written by another thread / block since the prior load).

Design choices

  • Top-level qd.volatile_load rather than qd.simt.grid.volatile_load -- matches qd.atomic_* placement and is consistent with how callers will pair the two ops in spin-wait code.
  • Flag on GlobalLoadStmt rather than a dedicated VolatileGlobalLoadStmt -- minimal blast radius. Only two transforms (cache_loop_invariant, simplify) and three codegen backends needed to learn the flag; everything else handles is_volatile=false (the default) unchanged.
  • volatile_store deferred -- the issue is read-only and can be paired in a follow-up PR if Alan / maintainers want symmetry. No commitment either way -- happy to add it here on request.

Test plan

tests/python/test_volatile_load.py (9 tests, all pass on the cluster on x64 / cuda / vulkan):

  • test_volatile_load_basic_value -- functional smoke on every backend (catches gross plumbing bugs).
  • test_volatile_load_emits_volatile_marker -- IR-level: asserts global load volatile appears in dumped IR on every backend (the primary signal that is_volatile survived the transform pipeline and reached codegen).
  • test_volatile_load_survives_loop_invariant_caching -- regression: kernel where a non-volatile load would be a hoist target, asserts the value is read correctly.
  • test_volatile_load_rejects_non_lvalue / test_volatile_load_rejects_bare_field -- frontend guards mirror qd.atomic_cas.

Sanity-checked the broader test_atomic / test_simt / test_offline_cache suite on the cluster: 1183 pass, 18 fail. All 18 failures reproduce on main without these changes (pre-existing f16-precision flake on test_atomic_float_ops[cuda-f16-sub] -- 3-of-5 attempts fail on main; Vulkan shaderSubgroupExtendedTypes validation issues on 64-bit subgroup ops -- correlates with the cluster Vulkan driver's missing extension, unrelated to this change).

Cluster GPU coverage: x64 + cuda + vulkan (cluster has no AMDGPU / Metal hardware). AMDGPU lowering is identical to CUDA via the shared TaskCodeGenLLVM::create_global_load; Metal goes through the SPIR-V path tested on Vulkan plus the same MemoryAccessVolatileMask lowering MoltenVK already consumes.

Made with Cursor

Issue: spin-wait patterns like

    while flags[prev] == STATE_INVALID:
        pass

are undefined at the LLVM IR / SPIR-V level: the compiler may hoist the load
out of the loop, turning the spin into an infinite loop.  The portable
workarounds (`grid.mem_fence()` inside the loop, or `atomic_add(flags, 0)`)
are correct but pay an order-of-magnitude perf tax over a real volatile read.

Add `qd.volatile_load(target)` -- a top-level frontend primitive (alongside
`qd.atomic_*`) that maps to a `GlobalLoadStmt` carrying a new `is_volatile`
flag.  Codegen on every backend:

  * CUDA / AMDGPU: LLVM `LoadInst::setVolatile(true)`, lowering to
    `ld.volatile.global` (PTX) / unhoistable `global_load_*` (AMDGPU).  CUDA
    additionally suppresses the `__ldg` / `!invariant.load` read-only-cache
    fast path for volatile loads (the two are contradictory).

  * Vulkan / Metal: SPIR-V `OpLoad` with the `Volatile` `MemoryAccess` mask
    via a new `IRBuilder::load_variable_volatile` helper.  Per-load opt-in
    on top of the existing Metal-global `use_volatile_buffer_access_` flag.

Transforms guarded:
  * `cache_loop_invariant_global_vars`: skip volatile loads (would hoist).
  * `simplify`: skip the redundant-load search for volatile loads (the cell
    may have been written by another thread / block since the prior load).

Added: `quadrants/inc/expressions.inc.h::VolatileLoadExpression`,
`quadrants/python/export_lang.cpp::expr_volatile_load`,
`python/quadrants/lang/ops.py::volatile_load`, and
`tests/python/test_volatile_load.py` (functional smoke + IR-level
`global load volatile` marker check on every supported arch + frontend
guard tests).

API choice: top-level `qd.volatile_load` (matches `qd.atomic_*` placement).
IR shape: flag on `GlobalLoadStmt` (minimal blast radius vs. a dedicated
stmt class).  `volatile_store` deferred -- the issue is read-only and can
be paired in a follow-up PR if Alan / maintainers want symmetry.

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💡 Codex Review

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Reviewed commit: c5049efa20

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"qd.volatile_load() requires a global lvalue (field / ndarray subscript); "
"function-scope local arrays are not visible to other threads.");
}
auto load_stmt = std::make_unique<GlobalLoadStmt>(ptr_stmt, /*is_volatile=*/true, dbg_info);

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P2 Badge Preserve volatility when scalarizing tensor loads

When qd.volatile_load() is used on a tensor-valued field or ndarray element, this creates a volatile GlobalLoadStmt, but the existing scalarization paths for tensor GlobalLoadStmts construct replacement element loads with the default constructor, so is_volatile is lost before codegen. In that scenario (for example qd.volatile_load(vec_field[i])), the emitted scalar loads can still be hoisted/merged, which breaks the documented volatile semantics for the returned value.

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// -- mirroring `flatten_global_load` but with the volatile bit set. Local-array sources are rejected: a
// function-scope alloca cannot be observed by another thread, so a volatile load there would be meaningless.
Stmt *ptr_stmt = flatten_lvalue(src, ctx);
if (ptr_stmt->is<AllocaStmt>()) {

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P2 Badge Reject local tensor element lvalues

This only rejects a bare AllocaStmt, but indexing a function-local tensor/vector produces a MatrixPtrStmt whose origin is the local alloca, so qd.volatile_load(v[0]) bypasses the intended local-array rejection and is lowered as a global load from a local pointer. That contradicts the new API contract that function-scope local arrays are rejected and can lead to invalid lowering/codegen instead of a user-facing error.

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"atomic_mul",
"atomic_exchange",
"atomic_cas",
"volatile_load",

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P2 Badge Add user docs for the new public API

AGENTS.md says public API changes must have corresponding end-user documentation under docs/, but this commit exposes a new qd.volatile_load API via __all__ without any docs/ changes. Users relying on the published docs will not learn the required usage constraints or when to choose this primitive over fences/atomics.

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Adds a `qd.volatile_load(target)` section to `docs/source/user_guide/atomics.md`
covering semantics, per-backend lowering (LLVM `load volatile` for CPU / CUDA /
AMDGPU; SPIR-V `OpLoad` with `Volatile` MemoryAccess for Vulkan / Metal), the
suppressed transforms (`cache_loop_invariant_global_vars`, `simplify` redundant-
load elimination, CUDA `__ldg` / `!invariant.load`), the canonical spin-wait
pattern, and the producer-side pairing requirements.

Also updates `docs/source/user_guide/grid.md` "Spin-wait gotcha" to recommend
`qd.volatile_load` as the cheapest cross-backend spelling, demoting the
`grid.mem_fence()` and `atomic_or(..., 0)` workarounds to legacy idioms (still
correct, but pay a per-iteration fence / RMW tax that volatile-load avoids).
Reviewer feedback: the jargon "spelling" (= different syntactic ways of writing
the same thing) is opaque to non-compiler-folks. Swap for "approach" everywhere
in the volatile_load docs. Leaves the pre-existing "Scope spelling in the IR"
table header in atomics.md alone — that one literally means "how the scope is
spelled out as IR text" (e.g. `seq_cst syncscope("agent")`).
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`tests/python/test_api.py::test_api[arch=*-quadrants]` is a frozen-allowlist
check that the public top-level symbols of the `quadrants` module match the
hard-coded list in this file. Adding `qd.volatile_load` to the public API in
`python/quadrants/lang/ops.py`'s `__all__` therefore requires a one-line
addition to the allowlist; without it the test fails with `expected` / `actual`
diff of exactly `'volatile_load'` (caught by CI on PR #702).
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…sing test

Three independent CI fixes for PR #702:

- clang-tidy: mark VolatileLoadExpression's single-arg constructor `explicit`
  to satisfy google-explicit-constructor (treated as error in CI).
- linters (black + clang-format): apply the exact reformatting CI's diff
  suggested -- collapse the multi-line `impl.expr_init(...)` call in
  python/quadrants/lang/ops.py::volatile_load, and re-indent the ternary in
  quadrants/codegen/spirv/spirv_codegen.cpp::TaskCodegen::load_buffer.
- coverage bot: add tests/python/test_volatile_load.py::
  test_volatile_load_rejects_local_array, exercising the C++-only AllocaStmt
  rejection in VolatileLoadExpression::flatten (a function-scope local tensor
  passes the two Python guards -- it's an lvalue and not a Field -- so this
  path is reachable only via the C++ check, which had no test).
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LGTM — clean design, well-documented, good test coverage. No concerns.

@hughperkins hughperkins merged commit 47494ea into main May 18, 2026
56 checks passed
@hughperkins hughperkins deleted the hp/volatile-load branch May 18, 2026 13:45
npoulad1 added a commit to ROCm/quadrants that referenced this pull request Jun 8, 2026
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* [AutoDiff] Autodiff 4: Mark rsqrt as non-linear for adstack promotion (Genesis-Embodied-AI#503)

* [AutoDiff] Autodiff 5: Fix adjoint-alloca placement for GlobalLoads outside the current range-for (Genesis-Embodied-AI#496)

* [AutoDiff] Autodiff 6: Adstack regression tests (Genesis-Embodied-AI#491)

* [AutoDiff] Autodiff 7: Fix header size in AdStackAllocaStmt to match u64 runtime layout (Genesis-Embodied-AI#534)

* [AutoDiff] Autodiff 8: Surface LLVM adstack push/pop overflow as a Python exception (Genesis-Embodied-AI#535)

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* [AutoDiff] Autodiff 10: Implement adstack for SPIR-V (Genesis-Embodied-AI#490)

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* [AutoDiff] Autodiff 14: Resolve bounded-inner-loop adstacks without default_ad_stack_size fallback (Genesis-Embodied-AI#539)

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* [AutoDiff] Autodiff 16: Resolve reverse-mode adstack depths per-launch via runtime-evaluated SizeExpr (Genesis-Embodied-AI#543)

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* [Bug] Fix: promote Ndarray to AnyArray in build_Name for flattened struct fields (Genesis-Embodied-AI#592)

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* [AutoDiff] Disable EliminateRecomputableAdStackPushes pending mutated-SNode chain-leaf fix (Genesis-Embodied-AI#633)

* [AutoDiff] Adstack chain-clone safety: mutated-SNode leaf reject + load_top consumer-aware guard (Genesis-Embodied-AI#634)

* [Docs] Add user-guide page for qd.simt.block.* primitives (Genesis-Embodied-AI#638)

* [Docs] Expand qd.simt.subgroup user-guide page to cover every op (Genesis-Embodied-AI#639)

* [Perf] Streams 1-4 (Genesis-Embodied-AI#410)

* [Docs] Add user-guide page for matrix decompositions and solvers (Genesis-Embodied-AI#643)

* [Bug] Revert "[Perf] Streams 1-4 (Genesis-Embodied-AI#410)" (Genesis-Embodied-AI#650)

* [Docs] Add user-guide page for atomics and bit operations (Genesis-Embodied-AI#640)

* [Docs] Add user-guide page for qd.simt.grid.* primitives (Genesis-Embodied-AI#641)

* [AutoDiff] Adstack max-reducer: parallel multi-axis MaxOverRange dispatch (Genesis-Embodied-AI#635)

* [AMDGPU] Fix amdgpu parallel rand init (Genesis-Embodied-AI#658)

* [Perf] Adstack: skip max-reducer recognizer on CPU + lift host-eval cap (Genesis-Embodied-AI#655)

* [Perf] Re-land Streams 1-4 with bug fixes (Genesis-Embodied-AI#653)

* [AMDGPU] Apply device_memory_GB=0.3 cap to AMDGPU tests (Genesis-Embodied-AI#659)

* [Perf] Per-launch host sync: drop wait_idle on SPIR-V, pin stream and drop stream_synchronize on CUDA/AMDGPU (Genesis-Embodied-AI#654)

* [AMDGPU] Unload hipModule_t in JITModuleAMDGPU destructor (Genesis-Embodied-AI#660)

* [AMDGPU] Trim default mempool on qd.reset() (Genesis-Embodied-AI#669)

* [AMDGPU] Hoist rand-state buffer to process lifetime (Genesis-Embodied-AI#668)

* [Streams] Use events for streams serialization on AMDGPU and CUDA (Genesis-Embodied-AI#667)

* [Perf] Adstack max-reducer: launch cache + zero-copy result map; content-stable registry_id (Genesis-Embodied-AI#671)

* [SPIR-V] dispatch_max_reducers: register each task with the real kernel name (Genesis-Embodied-AI#675)

* [AutoDiff] Debug-mode field/grad/dual: dtype, layout, and access-time invariants (Genesis-Embodied-AI#677)

* [Docs] Add user-guide page for qd.algorithms.* device-wide algorithms (Genesis-Embodied-AI#642)

Co-authored-by: alanray-tech <alan.ray@genesis-ai.company>

* [Docs] Doc for existing atomics: switch support table to per-backend columns (Genesis-Embodied-AI#657)

Co-authored-by: alanray-tech <alan.ray@genesis-ai.company>

* [GPU] Cross gpu atomics (Genesis-Embodied-AI#666)

Co-authored-by: alanray-tech <alan.ray@genesis-ai.company>

* [GPU] Make block operations portable cross-gpu (Genesis-Embodied-AI#664)

* [Perf] CPU LLVM adstack-cache: skip per-launch bump-writes + ndarray_shapes capture on forward-only handles (Genesis-Embodied-AI#685)

* [GPU] Cross-GPU for grid ops (Genesis-Embodied-AI#670)

* [Math] Make bitop operations portable cross-gpu (Genesis-Embodied-AI#662)

* [AMDGPU] Always use wave64, on both RDNA and CDNA (Genesis-Embodied-AI#687)

* [AMDGPU] Use syncscope("agent") for atomix xor to avoid CAS livelock (Genesis-Embodied-AI#672)

* [GPU] New bit ops for QIPC (Genesis-Embodied-AI#679)

* [GPU] Subgroup ops cross-gpu (Genesis-Embodied-AI#665)

* [Graph] Rename CUDA Graph to Graph in docs (Genesis-Embodied-AI#691)

* [SPIR-V] Fix FIFO-queue ordering when sharing command queue. (Genesis-Embodied-AI#694)

* [Atomics] New QIPC ops for atomics (Genesis-Embodied-AI#690)

* Pass dataclass sub-structs into qd.func (Genesis-Embodied-AI#698)

* [AMDGPU] HIP graph runtime support for @qd.kernel(graph=True) (Genesis-Embodied-AI#692)

* [CI] Add per-file timing report to Mac Metal test job (Genesis-Embodied-AI#695)

Co-authored-by: Cursor <cursoragent@cursor.com>

* [CI] Enable kernel disk cache during tests (Genesis-Embodied-AI#696)

* [Math] New QIPC ops for single-threaded linalg (Genesis-Embodied-AI#683)

* [BREAKING][GPU] New QIPC ops for subgroups (Genesis-Embodied-AI#676)

* [GPU] New QIPC ops for block (Genesis-Embodied-AI#684)

* [GPU] New device-level ops for QIPC (Genesis-Embodied-AI#693)

* [algorithms] PrefixSumExecutor: drop unused GRID_SZ local (Genesis-Embodied-AI#701)

* [block] sync(): fix unsupported-arch error message (Genesis-Embodied-AI#700)

* [volatile_load] add qd.volatile_load primitive (closes Genesis-Embodied-AI#648) (Genesis-Embodied-AI#702)

* [AutoDiff] Reject recycled identity_key in AdStackCache::register_adstack_sizing_info (Genesis-Embodied-AI#708)

* [Vulkan] Declare GroupNonUniform SPIR-V caps and enable shaderSubgroupExtendedTypes (Genesis-Embodied-AI#707)

* Fix duplicate HIP graph driver-function declarations after v1.0.0 merge

The amd-integration fork had cherry-picked the HIP graph driver functions
(graph_create / graph_destroy / graph_add_kernel_node / graph_instantiate /
graph_exec_destroy / graph_launch), and upstream v1.0.0 added the same set.
The per-file 3-way merge appended both copies into
amdgpu_driver_functions.inc.h, producing redeclaration errors that broke the
AMDGPU RHI/runtime compile. Drop the upstream duplicate block; the signatures
are identical to the fork's existing declarations.

Co-authored-by: Cursor <cursoragent@cursor.com>

* Fix AMDGPU launcher coherence and num_instructions visibility after v1.0.0 merge

- kernel_launcher.cpp: the 3-way merge spliced upstream v1.0.0's launch_llvm_kernel
  rewrite (ephemeral arg/context buffers, explicit-stream path, AmdgpuDefaultStream
  PinGuard) onto the AMD fork's kernarg-by-value + persistent-scratch design,
  leaving references to undefined `ephemeral_context_ptr`. Restore the fork's
  coherent launch_llvm_kernel verbatim; it calls the (already merged) enhanced
  launch_offloaded_tasks, which keeps the max-reducer dispatch and stream-parallel
  groups adapted onto the AMD launch path.
- llvm_context.h: both the fork and upstream added `num_instructions`; the merge
  kept upstream's private placement, but the AMDGPU codegen force-inline heuristic
  calls it statically from outside the class. Move it back to the public section.

Co-authored-by: Cursor <cursoragent@cursor.com>

* Restore async result D2H and hoist kernarg vectors in AMDGPU launcher

The v1.0.0 merge resolution regressed two amd-integration baseline
optimizations in launch_llvm_kernel / launch_offloaded_tasks:

  - The per-launch result-buffer copy was a blocking memcpy_device_to_host,
    forcing a host stall on every value-returning launch and serializing the
    GPU pipeline. Restore the async D2H (the caller synchronizes lazily when it
    needs the value); external-array transfers still stream_synchronize once
    before reading back.

  - launch_task constructed the kernarg std::vectors from initializer lists
    ({kernarg_payload} / {kernarg_size}) on every dispatch (heap alloc + free
    per launch). Hoist arg_ptrs/arg_sizes out of the per-task launch and reuse.

Co-authored-by: Cursor <cursoragent@cursor.com>

* amdgpu: default to LDS permlane64 emulation; drop host-x86 barrier asm on retarget

Two AMDGPU JIT-compile crashes surfaced after the v1.0.0 merge pulled in the QIPC subgroup
ops (Genesis-Embodied-AI#676), which made the rigid constraint solver's wave-cooperative reductions route through
`amdgpu_cross_half_shuffle_i32`. Both manifested as a SIGSEGV inside
`llvm::SIInstrInfo::getInstSizeInBytes` during `JITSessionAMDGPU::compile_module_to_hsaco`
(i.e. at first kernel launch), and reproduce on gfx942 / MI300X. Baseline 0.4.6 never emitted
these constructs, which is why it was unaffected.

1. Native `llvm.amdgcn.permlane64` lowering crashes the bundled LLVM 22.1.0 AMDGPU backend.
   Default `amdgpu_permlane64` to the existing LDS-roundtrip software emulation on every target
   (it produces identical results). Add `QD_AMDGPU_USE_NATIVE_PERMLANE64=1` to opt back into the
   native instruction once the backend bug is fixed; the old `QD_AMDGPU_FORCE_PERMLANE64_FALLBACK`
   is now the default and still honored. This is the actual crash fix.

2. The runtime module is compiled by the host x86_64 clang and only retargeted to amdgcn here, so
   `amdgpu_cross_half_shuffle_i32`'s `__asm__ volatile("" : "+v"(byte))` optimization barrier carries
   x86 flag clobbers (`~{dirflag},~{fpsr},~{flags}`) that are meaningless on AMDGPU. The IR verifies
   but the empty-body INLINEASM is invalid on the amdgcn target. Neutralize empty-body barrier asm
   during retarget (forward the tied value, then erase) so no stale host asm reaches codegen. On the
   wave64 targets we ship `ds_bpermute` already addresses the full wave, so the hint is a no-op.

Co-authored-by: Cursor <cursoragent@cursor.com>

* style: apply clang-format (v19.1.7) to AMDGPU fn_attrs and launcher sources

CI pre-commit's clang-format hook reformatted these files (long
declarations/lambda signatures collapsed onto single lines per the repo's
clang-format config). Apply the same formatting so the hook passes.

No functional changes.

Co-authored-by: Cursor <cursoragent@cursor.com>

* fix(amdgpu): use CreateNeg for branchless i32 sgn instead of CreateSub(0, input)

clang-tidy (modernize-use-nullptr, -warnings-as-errors) flagged
`builder->CreateSub(0, input)` in the i32 sgn path: the literal `0` binds to
the `llvm::Value*` LHS parameter as a null pointer, not an integer zero.
Replace with `builder->CreateNeg(input)`, which emits `0 - input` with a proper
zero constant -- identical intended semantics, and clang-tidy clean.

Co-authored-by: Cursor <cursoragent@cursor.com>

---------

Co-authored-by: Robert Dazi <14996868+v01dXYZ@users.noreply.github.com>
Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
Co-authored-by: Hugh Perkins <hughperkins@gmail.com>
Co-authored-by: Alexis DUBURCQ <alexis.duburcq@gmail.com>
Co-authored-by: hugh <hugh@slurm-login-0.slurm-login.tenant-slurm.svc.cluster.local>
Co-authored-by: alanray-tech <alan.ray@genesis-ai.company>
Co-authored-by: alanray-tech <alanray-tech@users.noreply.github.com>
Co-authored-by: root <root@rtx-209-201.slurm-compute.tenant-slurm.svc.cluster.local>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Johnny <johnnynuca14@gmail.com>
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[Feature] Add volatile_load primitive for spin-wait patterns

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