Skip to content

v3.0.0#40

Merged
Paebbels merged 5 commits into
mainfrom
dev
Jun 28, 2026
Merged

v3.0.0#40
Paebbels merged 5 commits into
mainfrom
dev

Conversation

@Paebbels

@Paebbels Paebbels commented May 14, 2026 •
edited
Loading

Copy link
Copy Markdown
Member

Caution

⚠️ This release contains breaking changes! ⚠️

The maintainers have decided to use the v3.0.0 release for major changes on component, generic, port and type names. This will harmonize the interfaces across all IP cores and allows the PoC-Library to grow future without contradictions in its naming style.

As PoC is huge, code snippets might have been overlooked and a bad decision was taken. This can be adjusted in an upcoming v4.0.0 release, but with a minimal impact compared to the v3.0.0 release.

New Features

  • PoC.bus.axi4:
    • Added axi4_Mux
    • Added axi4_DeMux
    • Added axi4_Sink
  • PoC.bus.axi4lite:
    • Added axi4lite_DeMux
  • PoC.bus.axi4stream:
    • Added axi4stream_Pause
  • PoC.dstruct:
    • Added dstruct_OutOfOrderBuffer
  • Added TCL script for post-write-bitstream to emit an XSA file.
  • Improved regression.tcl and TCL helper file poc.tcl:
    • Integrated generation of local_configuration.vhdl into poc.tcl for regression test.
      No manual file copy or sed necessary.
    • Allow running regression.tcl for single steps or steps from a certain level.
      Levels are: all, osvvm, poc, test
    • Mechanisms in regression.tcl can be reused in any outer repository or project using the PoC-Library.

Note

PoC v3.0.0 has now >200 IP cores.

Changes

  • ⚠️ Cleanup of entity names and interfaces
    • ⚠️ This also implies changed file names.
  • ⚠️ Renamed my_config.vhdl to project_configuration.vhdl (should be version controlled)
  • ⚠️ Renamed my_project.vhdl to local_configuration.vhdl (local to a specific PC)
  • Moved axi4lite entities from PoC.bus.axi4.axi4lite to PoC.bus.axi4lite.
  • Moved axi4stream entities from PoC.bus.axi4.axi4stream to PoC.bus.axi4stream.
  • Removed unused constant MY_OPERATING_SYSTEM.
  • Removed pyIPCMI files.
  • Removed trailing whitespaces.
  • Removed editor settings at beginning of source files.

Bug Fixes

  • Many
  • Removed unused signals.
  • Removed unused declarations.
  • Removed unused attributes.
  • Converted unmodified variables to constants.
  • Removed unused parameters from functions.
  • Removed redundant others cases.
  • Removed unused signals from sensitivity lists.
  • Updated component declarations from entity declarations.

Documentation

  • Replaced repository URLs to VLSI-EDA/PoC by VHDL/PoC.
  • Updates ReST files according to code changes.

Tests

  • Disabled PASSED and INFO messages in OSVVM testcases.
  • Added testcases for new modules
  • Add more testcases.

Note

PoC v3.0.0 has now 52 OSVVM testcases.

Pipeline

Related Issues and Pull-Requests

@Paebbels Paebbels self-assigned this May 14, 2026
@Paebbels Paebbels added the CI: GitHub Actions GitHub Actions workflow (CI pipeline) label May 14, 2026
@Paebbels
Paebbels changed the base branch from master to main June 16, 2026 17:24
@Paebbels Paebbels changed the title v2.4.0 v3.0.0 Jun 16, 2026
@Paebbels Paebbels added this to the v3.0.0 milestone Jun 16, 2026
This was linked to issues Jun 16, 2026
Remove types and functions only needed for VHDL < 2008 #12
Open
Drop Xilinx ISE Support #9
Open
@Paebbels Paebbels added Enhancement Code improvements. AXI4 AXI4 latest issue. See also AXI4-Lite and AXI4-Stream AXI4-Lite PoC.bus.* Chip internal protocols. ThirdParty: OSVVM OSVVM related. labels Jun 16, 2026
@stefanunrein @Paebbels
@weilanad @Asif71
AXI4/AXI4-Lite multiplexers and demultiplexers (#42)
b8eed65 
* * Refactor PoC file names and signal names
* Add AXI components
* Add more test cases

Co-Authored-By: Patrick Lehmann <Paebbels@gmail.com>
Co-Authored-By: Adrian Weiland <adrian.weiland@plc2.de>
Co-Authored-By: Iqbal Asif <asif.iqbal@plc2.de>

* * use integer'image instead of to_string because GHDL can not determine overload
* disable axi4lite_OCRAM test bench for GHDL because llvm can not handle external names

* Apply suggestions from code review

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>

* Apply suggestions from code review

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>

* Some more naming fixes.

* replace all VLSI-EDA URL's with github.com/VHDL/PoC

* cleanup of filenames for missed components

* separate file list for ddrio

* rename mem files in build.pro

* apply suggestions from review

* Update docs/IPCores/cache/index.rst

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
(cherry picked from commit d543af4)

# Conflicts:
#	docs/IPCores/cache/index.rst

* renaming

* renaming

* fix compile order, spelling
updated regression tcl for with possibility to run only selected steps, added updated ci yaml with stages

* Updated interfaces in _wf (_WriteFirst) OCRAMs.

* Removed pyIPCMI configuration files.

* Adjusted port names in OCRAM simulation model.

* Use new regression.tcl with steps feature.

* Apply suggestions from code review

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Apply suggestions from code review 4

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Apply suggestion from @Paebbels
Apply suggestions from code review 3

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Apply suggestions from code review 2

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Apply suggestions from code review 1

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>

* Changed references to branch 'master' to 'main'.

* Apply suggestions from code review 2.1

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>

* Fixed ReST table.

* Run NVC on older Ubuntu 24.04 images.

* Rename BasicProc to ControlProc

* cleanup clock and reset name

* * remove py folder
* remove sim folder with old waveform config files
* rename My_config and my_project to project_configuration and local_configuration

* process name conflict

* add missing files

* rename axi4stream testcases

* renaming

* move arith test benches to correct named folders

* apply suggestions

* fix restructured text header underlines

* fix copyright

* fix log2ceil function to work until integer'high
fixes /issues/41

* Update tb/bus/axi4stream/DeMux/TC_DeMux_e.vhdl

(cherry picked from commit 9e61476)

* change myConfig and myProject in tcl scripting

* move poc.tcl to tools

* fix naming of axi4stream termination modules

* pass project root to poc-tcl scripting

* remove old config files

* remove test code from contributed test-case
Co-Authored-By: Markus Leiter <leiter@p2l2.com>

---------

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Co-authored-by: Adrian Weiland <adrian.weiland@plc2.de>
Co-authored-by: Iqbal Asif <asif.iqbal@plc2.de>
Co-authored-by: Patrick Lehmann <Patrick.Lehmann@plc2.de>
@Paebbels Paebbels linked an issue Jun 18, 2026 that may be closed by this pull request
log2ceil Implementation fails for 31 bit values #41
Closed
@stefanunrein @Paebbels @weilanad
More enhancements by @PLC2
41d05da 
* write local configuration automatically on initial regression run
* remove inner generate label
* update fifo-ic-git constraint to new generates
* fix variable direction for init mem file function
* fix paths for local and project config file
* beautify print
* FILL_STATE vs. FULL_STATE vs. FSTATE.
* Removed EMACS, vim/vi, Kate setting lines.
* remove temporary script for cleanup
* Cleaned up more findings found by Sigasi.
* Fixed more warnings reported by Sigasi.
* Fixes after removinbg unused code.
* Simplified GitLab-CI script.
* Fixed 'ram' signals to be VHDL-2008 compliant.
* Fix GitLab-CI pipeline.
* Disabled INFO and PASSED messages. Removed trailing whitespaces.
* * print message if local-file generation is skipped
* remove spaces for puts prefix for disabled and duplicate procedure
* Improve GitLab and GitHub pipelines.

---------

Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Co-authored-by: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Co-authored-by: Adrian Weiland <Adrian.Weiland@plc2.de>
@Paebbels @weilanad
Fix LuaLaTeX documentation flow (#44)
48d65ec 
* Bumped GitHub Action dependencies.
* Updated Unicode font and LuaLaTeX usage.
* initialize axi4 sink signals

---------

Co-authored-by: Adrian Weiland <adrian.weiland@plc2.de>
@Paebbels
Paebbels marked this pull request as ready for review June 28, 2026 22:05
@Paebbels
Paebbels merged commit b904027 into main Jun 28, 2026
64 of 66 checks passed
@Paebbels Paebbels mentioned this pull request Jun 28, 2026
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

@Paebbels Paebbels

Labels

AXI4-Lite AXI4 AXI4 latest issue. See also AXI4-Lite and AXI4-Stream CI: GitHub Actions GitHub Actions workflow (CI pipeline) Enhancement Code improvements. PoC.bus.* Chip internal protocols. ThirdParty: OSVVM OSVVM related.

Projects

None yet

Milestone

v3.0.0

Development

Successfully merging this pull request may close these issues.

Remove types and functions only needed for VHDL < 2008 Drop Xilinx ISE Support log2ceil Implementation fails for 31 bit values

2 participants

@Paebbels @stefanunrein