AXI4/AXI4-Lite multiplexers and demultiplexers#42
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* Add AXI components * Add more test cases Co-Authored-By: Patrick Lehmann <Paebbels@gmail.com> Co-Authored-By: Adrian Weiland <adrian.weiland@plc2.de> Co-Authored-By: Iqbal Asif <asif.iqbal@plc2.de>
…ne overload * disable axi4lite_OCRAM test bench for GHDL because llvm can not handle external names
Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
Co-authored-by: Patrick Lehmann <Paebbels@gmail.com> (cherry picked from commit d543af4) # Conflicts: # docs/IPCores/cache/index.rst
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updated regression tcl for with possibility to run only selected steps, added updated ci yaml with stages
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* remove sim folder with old waveform config files * rename My_config and my_project to project_configuration and local_configuration
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| variable myConfigFolder "../tb/common" | ||
| variable myConfigFile [file join $myConfigFolder "project_configuration_${::poc::boardName}.vhdl"] | ||
| variable myProjectFile [file join $myConfigFolder "local_configuration.vhdl"] |
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This needs to be adjusted too.
(cherry picked from commit 9e61476)
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# Conflicts: # .github/workflows/Simulate.yml
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| -- function log2ceil(arg : positive) return natural is | ||
| -- variable tmp : positive := 2; | ||
| -- variable log : natural := 1; | ||
| -- begin | ||
| -- if arg = 1 then | ||
| -- return 0; | ||
| -- end if; | ||
| -- | ||
| -- while arg > tmp loop | ||
| -- tmp := tmp * 2; | ||
| -- log := log + 1; | ||
| -- end loop; | ||
| -- return log; | ||
| -- end function; |
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This old code be removed.
@stefanunrein: Can we add @maleiter as a co-author?
Co-Authored-By: Markus Leiter <leiter@p2l2.com>
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/cc @weilanad, @JimLewis