Build SOF with Zephyr on i.MX #4217
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lgirdwood
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May 20, 2021
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Can we also add the imx Zephyr targets into the build script used by CI.
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Sure, I can do that, but shouldn't we wait for the Zephy PR be merged - #35467? So, I would add the imx8 target in xtensa-build-zephyr.sh, when I'll have the corresponding patch for sign.py from Zephyr. Otherwise, it will fail at: |
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Yes, sorry I was meaning to make the script build imx Zephyr as part of this PR. |
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dbaluta
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May 20, 2021
dbaluta
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May 20, 2021
dbaluta
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dbaluta
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dbaluta
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This was referenced May 21, 2021
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lgirdwood
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May 26, 2021
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LGTM, but I wont merge until NXP folks have aligned or merge it themselves.
Build SOF with Zephyr for i.MX platforms. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Zephyr already uses main() and has already performed a lot of initialization before entering SOF. Split initialization, for i.MX platforms, to make sure no operation is repeated. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Use the Zephyr sys/util.h when Zephyr RTOS is used. While here, remove sof/lib/cpu.h which is not used. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
When building SOF with Zephyr for i.MX the following additional adjustments, to the wrapper, are required: 1. include heapmem variable in .heap_mem section, otherwise the HEAP_SIZE is duplicated in two sections and the sdram0 region overflows; 2. no need to split heap into shared and unshared since we only have 1 DSP core; In this case, the kernel will never be built in a mode where all shared data is placed in multiprocessor-coherent (generally "uncached") memory. 3. use simple interrupt_get_irq() to get the Linux interrupt and later pass it to irq_steer; 4. use Xtensa timer, as we do now with SOF and XTOS. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
…CE not set When building SOF with Zephyr, for i.MX, we get the following error: undefined reference to `z_xtensa_cache_inv'. i.MX has only one DSP core, so CONFIG_KERNEL_COHERENCE is not set. Therefore include arch/xtensa/cache.h, where z_xtensa_cache_inv is defined and implemented, in cases when the kernel is not built in a mode where all shared data is placed in uncached memory. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
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dbaluta
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Jul 6, 2021
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LGTM, thanks Iulia! |
marc-hb
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This reverts the only line in commit 34bb9b7 / PR thesofproject#4217 that is not under some #ifdef IMX This avoids the following crash always happening on my Up Squared board on the second aplay command: [00022612] <err> os: ** FATAL EXCEPTION [00022612] <err> os: ** CPU 0 EXCCAUSE 13 (load/store PIF d{slot 33, seq=34} ata error) [00022612] <err> os: ** PC 0xbe00b7ed VADDR 0x9e08bbc4 [00022612] <err> os: ** PS 0x60a20 [00022612] <err> os: ** (INTLEVEL:0 EXCM: 0 UM:1 RING:0 {slot 37, seq=38} WOE:1 OWB:10 CALLINC:2) [00022612] <err> os: ** A0 0xbe00ba7e SP 0xbe0498e0 A2 0{slot 39, seq=40} x1fff A3 0x9e08bbc4 [00022612] <err> os: ** A4 0x4 A5 0xc1 A6 0x1b20 A7 0xb{slot 41, seq=42} e049b64 [00022612] <err> os: ** A8 0x7fff A9 0x7fff A10 0xe A11 0{slot 43, seq=44} x9e0732c2 [00022612] <err> os: ** A12 0x2 A13 0x182 A14 0x180 A15 0x6{slot 45, seq=46} 0 [00022612] <err> os: ** LBEG 0xbe01739c LEND 0xbe0173a6 LCO{slot 47, seq=48} UNT (nil) [00022612] <err> os: ** SAR 0x19 [00022612] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception{slot 50, seq=51} on CPU 0 [00022612] <err> os: Current thread: 0x9e075ca8 (unknown) [00022614] <err> os: Halting system
marc-hb
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Jul 10, 2021
| if (zone_is_cached(zone)) | ||
| return heap_alloc_aligned_cached(&sof_heap, 0, bytes); | ||
| else | ||
| return heap_alloc_aligned(&sof_heap, 8, bytes); |
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This line "reliably" crashes my Up Squared board on the second aplay command every time, see partial revert PR #4472
git bisect found this commit and then it was easy to identify this line because it seems to be the only one not IMX-specific.
Cc: @lyakh , @lgirdwood , @andyross
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Add support for i.MX to build Sound Open Firmware with Zephyr OS.
Please check each commit message.
With these commits I have a successful build.
I obtain the zephyr.ri image which boots the DSP and loads the topology.
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