Add periodic CI job to test off-by-default code

[BruceForstall]

There are several codes in the JIT that are currently off by default, but we would like to ensure they don't regress (too badly) before they are able to be enabled by default. Consider adding a regularly run (weekly?) AzDO pipeline that runs these.

E.g., EH WriteThru (#543 ), OSR (on stack replacement), guarded de-virtualization, the interpreter.

category:eng-sys
theme:testing
skill-level:beginner
cost:small

[BruceForstall]

cc @AndyAyersMS

[Gnbrkm41]

On a slightly unrelated note, having test configurations for different ISAs available (e.g. AVX2 / SSE41 / SSE2 / None) would be also great for testing System.Numerics namespace and various components that use HWIntrinsics in their implementations. They can be configured with COMPlus_Enable{ISA} environment variable:

runtime/src/coreclr/src/jit/jitconfigvalues.h

Lines 223 to 275 in 2f38f64

	#if defined(TARGET_AMD64) || defined(TARGET_X86)
	// Enable AVX instruction set for wide operations as default. When both AVX and SSE3_4 are set, we will use the most
	// capable instruction set available which will prefer AVX over SSE3/4.
	CONFIG_INTEGER(EnableHWIntrinsic, W("EnableHWIntrinsic"), 1) // Enable Base
	CONFIG_INTEGER(EnableSSE, W("EnableSSE"), 1) // Enable SSE
	CONFIG_INTEGER(EnableSSE2, W("EnableSSE2"), 1) // Enable SSE2
	CONFIG_INTEGER(EnableSSE3, W("EnableSSE3"), 1) // Enable SSE3
	CONFIG_INTEGER(EnableSSSE3, W("EnableSSSE3"), 1) // Enable SSSE3
	CONFIG_INTEGER(EnableSSE41, W("EnableSSE41"), 1) // Enable SSE41
	CONFIG_INTEGER(EnableSSE42, W("EnableSSE42"), 1) // Enable SSE42
	CONFIG_INTEGER(EnableAVX, W("EnableAVX"), 1) // Enable AVX
	CONFIG_INTEGER(EnableAVX2, W("EnableAVX2"), 1) // Enable AVX2
	CONFIG_INTEGER(EnableFMA, W("EnableFMA"), 1) // Enable FMA
	CONFIG_INTEGER(EnableAES, W("EnableAES"), 1) // Enable AES
	CONFIG_INTEGER(EnableBMI1, W("EnableBMI1"), 1) // Enable BMI1
	CONFIG_INTEGER(EnableBMI2, W("EnableBMI2"), 1) // Enable BMI2
	CONFIG_INTEGER(EnableLZCNT, W("EnableLZCNT"), 1) // Enable AES
	CONFIG_INTEGER(EnablePCLMULQDQ, W("EnablePCLMULQDQ"), 1) // Enable PCLMULQDQ
	CONFIG_INTEGER(EnablePOPCNT, W("EnablePOPCNT"), 1) // Enable POPCNT
	#else // !defined(TARGET_AMD64) && !defined(TARGET_X86)
	// Enable AVX instruction set for wide operations as default
	CONFIG_INTEGER(EnableAVX, W("EnableAVX"), 0)
	#endif // !defined(TARGET_AMD64) && !defined(TARGET_X86)
	CONFIG_INTEGER(EnableEHWriteThru, W("EnableEHWriteThru"), 0) // Enable the register allocator to support EH-write thru:
	// partial enregistration of vars exposed on EH boundaries
	// clang-format off
	#if defined(TARGET_ARM64)
	CONFIG_INTEGER(EnableHWIntrinsic, W("EnableHWIntrinsic"), 1)
	CONFIG_INTEGER(EnableArm64Aes, W("EnableArm64Aes"), 1)
	CONFIG_INTEGER(EnableArm64Atomics, W("EnableArm64Atomics"), 1)
	CONFIG_INTEGER(EnableArm64Crc32, W("EnableArm64Crc32"), 1)
	CONFIG_INTEGER(EnableArm64Dcpop, W("EnableArm64Dcpop"), 1)
	CONFIG_INTEGER(EnableArm64Dp, W("EnableArm64Dp"), 1)
	CONFIG_INTEGER(EnableArm64Fcma, W("EnableArm64Fcma"), 1)
	CONFIG_INTEGER(EnableArm64Fp, W("EnableArm64Fp"), 1)
	CONFIG_INTEGER(EnableArm64Fp16, W("EnableArm64Fp16"), 1)
	CONFIG_INTEGER(EnableArm64Jscvt, W("EnableArm64Jscvt"), 1)
	CONFIG_INTEGER(EnableArm64Lrcpc, W("EnableArm64Lrcpc"), 1)
	CONFIG_INTEGER(EnableArm64Pmull, W("EnableArm64Pmull"), 1)
	CONFIG_INTEGER(EnableArm64Sha1, W("EnableArm64Sha1"), 1)
	CONFIG_INTEGER(EnableArm64Sha256, W("EnableArm64Sha256"), 1)
	CONFIG_INTEGER(EnableArm64Sha512, W("EnableArm64Sha512"), 1)
	CONFIG_INTEGER(EnableArm64Sha3, W("EnableArm64Sha3"), 1)
	CONFIG_INTEGER(EnableArm64AdvSimd, W("EnableArm64AdvSimd"), 1)
	CONFIG_INTEGER(EnableArm64AdvSimd_v81, W("EnableArm64AdvSimd_v81"), 1)
	CONFIG_INTEGER(EnableArm64AdvSimd_Fp16, W("EnableArm64AdvSimd_Fp16"), 1)
	CONFIG_INTEGER(EnableArm64Sm3, W("EnableArm64Sm3"), 1)
	CONFIG_INTEGER(EnableArm64Sm4, W("EnableArm64Sm4"), 1)
	CONFIG_INTEGER(EnableArm64Sve, W("EnableArm64Sve"), 1)
	#endif // defined(TARGET_ARM64)

Often those APIs take different paths depending on the ISA levels available that are otherwise unreachable and will get eliminated by the JIT. Ensuring those fallback paths don't fail with AVE / incorrect behaviours would be nice. I believe currently we don't do that.

[BruceForstall]

@Gnbrkm41 The "runtime-coreclr jitstress-isa-x86" pipeline (https://dev.azure.com/dnceng/public/_build?definitionId=664) should cover this.

[BruceForstall]

Fixed by #33709

(Note, we could still add more to the pipeline as appropriate, e.g., interpreter, if it is brought back to life).