dw-dma: fix the lli corruption issue

[keyonjie]

dw-dma: change to use runtime_shared heap for lli buffer

The lli structs are used by both DSP and DMAC, allocate them from the
runtime_shared heap to avoid being corrupted by cache writing back.

This helps to fix a lot of DMA xrun issue according to the validation.

Signed-off-by: Keyon Jie yang.jie@linux.intel.com

[lgirdwood]

@keyonjie looks like we need to make this a CONFIG option. CONFIG_DMA_DW_LLI_CACHE_LINE_SIZE(force LLI to be cache line size) and CONFIG_DMA_DW_LLI_PADDING (force LLI to be padded in LLI blocks). This way we can disable on legacy platforms and use only on Intel CAVS HW.

[keyonjie]

@lgirdwood I didn't have intent to make this get merged to any branch, I will go forward to pursue explicit root cause of it.

[lgirdwood]

Thanks @keyonjie , we will also need a version for main branch.

[fuyuntsuo]

Just wondering why only LLI struct needs to be aligned with the cache line size

[lgirdwood]

Just wondering why only LLI struct needs to be aligned with the cache line size

The IO buses that connect all the IP will have constraints around bus arbitration and data transfers and the DW DMAC IP config may be configured with a min transfer size R and W of 128 bytes on TGL. No impact on audio transfers are buffers/periods are all > 128 bytes.

@keyonjie this also makes me think we may need a constraint on the audio buffer sizes on TGL for DW DMA so period sizes and addresses are aligned to 128 bytes (which I think is true today in all topologies but not enforced).

[plbossart]

Just wondering why only LLI struct needs to be aligned with the cache line size

The IO buses that connect all the IP will have constraints around bus arbitration and data transfers and the DW DMAC IP config may be configured with a min transfer size R and W of 128 bytes on TGL. No impact on audio transfers are buffers/periods are all > 128 bytes.

@keyonjie this also makes me think we may need a constraint on the audio buffer sizes on TGL for DW DMA so period sizes and addresses are aligned to 128 bytes (which I think is true today in all topologies but not enforced).

It would be surprising, with our use of a 1ms tick it's not clear how the DMA sizes might be aligned to 128 bytes. Edit: the address could be fine, it's the size that would seem problematic.

[lgirdwood]

It would be surprising, with our use of a 1ms tick it's not clear how the DMA sizes might be aligned to 128 bytes. Edit: the address could be fine, it's the size that would seem problematic.

Just checked topology, the S32_LE stereo comply with the size, but S16_LE don't (and work). My thinking now is that the LLI writeback uses a HW defined DMAC channel, wordsize, burstsize, and block size (meaning we only see this for LLI copies).

[fuyuntsuo]

Just wondering why only LLI struct needs to be aligned with the cache line size

The IO buses that connect all the IP will have constraints around bus arbitration and data transfers and the DW DMAC IP config may be configured with a min transfer size R and W of 128 bytes on TGL. No impact on audio transfers are buffers/periods are all > 128 bytes.

@keyonjie this also makes me think we may need a constraint on the audio buffer sizes on TGL for DW DMA so period sizes and addresses are aligned to 128 bytes (which I think is true today in all topologies but not enforced).

Thanks. Just find a related PR #3645 and learn that the lli buffer is shared by both DSP and DMA controller.