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Merged
lgirdwood merged 7 commits into from
Apr 13, 2021
Merged

topology: add ADL SoundWire support #3978

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00b5628
topology: soundwire: remove hard-coded hex values
plbossart Mar 29, 2021
abc32bf
topology: soundwire: add 'NOJACK' option
plbossart Mar 29, 2021
d139146
topology: soundwire: add macros for link numbers
plbossart Mar 29, 2021
1160d18
topology: soundwire: use macros for dailink names
plbossart Mar 29, 2021
05e01b0
topology: align SoundWire topologies with the use of macros
plbossart Mar 29, 2021
a1b7c80
topology: add adl.m4
plbossart Mar 29, 2021
898be9c
topology: add ADL SoundWire topologies
plbossart Mar 29, 2021
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12 changes: 8 additions & 4 deletions tools/topology/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -89,10 +89,14 @@ set(TPLGS
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-cml-rt711-rt1308-mono-rt715\;-DPLATFORM=cml\;-DMONO"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-cml-rt711-rt1308-rt715\;-DPLATFORM=cml"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-icl-rt711-rt1308-rt715\;-DPLATFORM=icl"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-mono-rt715\;-DPLATFORM=tgl\;-DMONO"
"sof-tgl-rt715-rt711-rt1308-hdmi\;sof-tgl-rt715-rt711-rt1308-mono\;-DPLATFORM=tgl"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-rt715\;-DPLATFORM=tgl"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1316-rt714\;-DPLATFORM=tgl"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-mono-rt715\;-DPLATFORM=tgl\;-DMONO\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DMIC_LINK=3"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt715-rt711-rt1308-mono\;-DPLATFORM=tgl\;-DMONO\;-DUAJ_LINK=1\;-DAMP_1_LINK=2\;-DMIC_LINK=0"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-rt715\;-DPLATFORM=tgl\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DAMP_2_LINK=2\;-DMIC_LINK=3"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1316-rt714\;-DPLATFORM=tgl\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DAMP_2_LINK=2\;-DMIC_LINK=3"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-adl-rt711-l0-rt1308-l12-rt715-l3\;-DPLATFORM=adl\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DAMP_2_LINK=2\;-DMIC_LINK=3"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-adl-rt711-l0-rt1316-l12-rt714-l3\;-DPLATFORM=adl\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DAMP_2_LINK=2\;-DMIC_LINK=3"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-adl-rt711-l0-rt1316-l13-rt714-l2\;-DPLATFORM=adl\;-DUAJ_LINK=0\;-DAMP_1_LINK=1\;-DAMP_2_LINK=3\;-DMIC_LINK=2"
"sof-icl-rt711-rt1308-rt715-hdmi\;sof-adl-rt1316-l2-mono-rt714-link0\;-DPLATFORM=adl\;-DMONO\;-DNOJACK\;-DAMP_1_LINK=2\;-DMIC_LINK=0"
"sof-cnl-rt5682-sdw2\;sof-cnl-rt5682-sdw2\;-DPLATFORM=cnl"
"sof-cml-rt5682\;sof-cml-rt5682\;-DPLATFORM=cml\;-DDMICPROC=eq-iir-volume\;-DDMIC16KPROC=eq-iir-volume"
"sof-cml-rt5682\;sof-whl-rt5682\;-DPLATFORM=whl\;-DDMICPROC=eq-iir-volume\;-DDMIC16KPROC=eq-iir-volume"
Expand Down
38 changes: 38 additions & 0 deletions tools/topology/platform/intel/adl.m4
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Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
#
# Tigerlake differentiation for pipelines and components
#

include(`memory.m4')

dnl Memory capabilities for different buffer types on Tigerlake
define(`PLATFORM_DAI_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_HOST_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_PASS_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))

# Low Latency PCM Configuration
W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "50000"'))

W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)

# Media PCM Configuration
W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "100000"'))

W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)

# Tone Signal Generator Configuration
W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "200000"'))

W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)

# DAI schedule Configuration - scheduled by IRQ
W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "5000"'))

W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)
61 changes: 45 additions & 16 deletions tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,18 @@ include(`sof/tokens.m4')
# Include Platform specific DSP configuration
include(`platform/intel/'PLATFORM`.m4')

ifdef(`UAJ_LINK',`',
`define(UAJ_LINK, `0')')

ifdef(`AMP_1_LINK',`',
`define(AMP_1_LINK, `1')')

ifdef(`AMP_2_LINK',`',
`define(AMP_2_LINK, `2')')

ifdef(`MIC_LINK',`',
`define(MIC_LINK, `3')')

DEBUG_START

dnl Configure demux
Expand Down Expand Up @@ -57,8 +69,11 @@ MUXDEMUX_CONFIG(demux_priv_3, 2, LIST(` ', `matrix1,', `matrix2'))
#
# Define the pipelines
#
ifdef(`NOJACK', `',
`
# PCM0 ---> volume ----> ALH 2 BE dailink 0
# PCM1 <--- volume <---- ALH 3 BE dailink 1
')
# PCM2 ---> volume ----> ALH 2 BE dailink 2
ifdef(`MONO', `',
`# PCM40 ---> volume ----> ALH 2 BE dailink 3')
Expand All @@ -73,6 +88,8 @@ dnl period, priority, core,
dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
dnl time_domain, sched_comp)

ifdef(`NOJACK', `',
`
# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
Expand All @@ -86,6 +103,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
2, 1, 2, s32le,
1000, 0, 0,
48000, 48000, 48000)
')

ifdef(`MONO',
`
Expand Down Expand Up @@ -151,37 +169,40 @@ dnl pipe id, dai type, dai_index, dai_be,
dnl buffer, periods, format,
dnl deadline, priority, core, time_domain)

ifdef(`NOJACK', `',
`
# playback DAI is ALH(SDW0 PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
1, ALH, 2, SDW0-Playback,
1, ALH, eval(UAJ_LINK * 256 + 2), `SDW'eval(UAJ_LINK)`-Playback',
PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

# capture DAI is ALH(SDW0 PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
2, ALH, 3, SDW0-Capture,
2, ALH, eval(UAJ_LINK * 256 + 3), `SDW'eval(UAJ_LINK)`-Capture',
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
')

# playback DAI is ALH(SDW1 PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
3, ALH, 0x102, SDW1-Playback,
3, ALH, eval(AMP_1_LINK * 256 + 2), `SDW'eval(AMP_1_LINK)`-Playback',
PIPELINE_SOURCE_3, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

ifdef(`NO_AGGREGATION',
`# playback DAI is ALH(SDW2 PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
4, ALH, 0x202, SDW2-Playback,
4, ALH, eval(AMP_2_LINK * 256 + 2), `SDW'eval(AMP_2_LINK)`-Playback',
PIPELINE_SOURCE_4, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)',
`ifdef(`MONO', `',
`DAI_ADD_SCHED(sof/pipe-dai-sched-playback.m4,
4, ALH, 0x202, SDW1-Playback,
4, ALH, eval(AMP_2_LINK * 256 + 2), `SDW'eval(AMP_1_LINK)`-Playback',
PIPELINE_SOURCE_4, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER,
PIPELINE_PLAYBACK_SCHED_COMP_3)
Expand All @@ -200,7 +221,7 @@ SectionGraph."PIPE_DEMUX" {
# capture DAI is ALH(SDW3 PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
5, ALH, 0x302, SDW3-Capture,
5, ALH, eval(MIC_LINK * 256 + 2), `SDW'eval(MIC_LINK)`-Capture',
PIPELINE_SINK_5, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

Expand All @@ -227,8 +248,13 @@ DAI_ADD(sof/pipe-dai-playback.m4,

# PCM Low Latency, id 0
dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)

ifdef(`NOJACK', `',
`
PCM_PLAYBACK_ADD(Jack Out, 0, PIPELINE_PCM_1)
PCM_CAPTURE_ADD(Jack In, 1, PIPELINE_PCM_2)
')

PCM_PLAYBACK_ADD(Speaker, 2, PIPELINE_PCM_3)
ifdef(`NO_AGGREGATION', `PCM_PLAYBACK_ADD(Speaker 2, 40, PIPELINE_PCM_4)',`')
PCM_CAPTURE_ADD(Microphone, 4, PIPELINE_PCM_5)
Expand All @@ -240,28 +266,31 @@ PCM_PLAYBACK_ADD(HDMI 3, 7, PIPELINE_PCM_8)
# BE configurations - overrides config in ACPI if present
#

ifdef(`NOJACK', `',
`
#ALH dai index = ((link_id << 8) | PDI id)
#ALH SDW0 Pin2 (ID: 0)
DAI_CONFIG(ALH, 2, 0, SDW0-Playback,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 2, 48000, 2)))
DAI_CONFIG(ALH, eval(UAJ_LINK * 256 + 2), 0, `SDW'eval(UAJ_LINK)`-Playback',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(UAJ_LINK * 256 + 2), 48000, 2)))

#ALH SDW0 Pin3 (ID: 1)
DAI_CONFIG(ALH, 3, 1, SDW0-Capture,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 3, 48000, 2)))
DAI_CONFIG(ALH, eval(UAJ_LINK * 256 + 3), 1, `SDW'eval(UAJ_LINK)`-Capture',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(UAJ_LINK * 256 + 3), 48000, 2)))
')

#ALH SDW1 Pin2 (ID: 2)
DAI_CONFIG(ALH, 0x102, 2, SDW1-Playback,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 0x102, 48000, 2)))
DAI_CONFIG(ALH, eval(AMP_1_LINK * 256 + 2), 2, `SDW'eval(AMP_1_LINK)`-Playback',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(AMP_1_LINK * 256 + 2), 48000, 2)))

ifdef(`NO_AGGREGATION',
`#ALH SDW2 Pin2 (ID: 3)
DAI_CONFIG(ALH, 0x202, 3, SDW2-Playback,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 0x202, 48000, 2)))',
DAI_CONFIG(ALH, eval(AMP_2_LINK * 256 + 2), 3, `SDW'eval(AMP_2_LINK)`-Playback',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(AMP_2_LINK * 256 + 2), 48000, 2)))',
`')

#ALH SDW3 Pin2 (ID: 4)
DAI_CONFIG(ALH, 0x302, 4, SDW3-Capture,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 0x302, 48000, 2)))
DAI_CONFIG(ALH, eval(MIC_LINK * 256 + 2), 4, `SDW'eval(MIC_LINK)`-Capture',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(MIC_LINK * 256 + 2), 48000, 2)))

# 3 HDMI/DP outputs (ID: 5,6,7)
DAI_CONFIG(HDA, 0, 5, iDisp1,
Expand Down
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