SCU and GPIO register modify

[Kenthliu]

Please help to change the below setting since there was a GPIO debouce issue.
1E6E20A8 bit24 =1
1E780048 bit0 = 1
1E78004C bit0 = 1
1E780058 = 75300h

[Kenthliu]

One more register. GPIOQ7 need to pull low when power on that make identify LED can be control.
1E780084 bit7 = 1
1E780080 bit7 = 0

[nkskjames]

@Kenthliu, you could make the change yourself so you could test as well. Change goes here: https://github.com/openbmc/linux/blob/dev-4.4/arch/arm/mach-aspeed/aspeed.c#L128

[Kenthliu]

Ok sure

[Kenthliu]

Done.
#78

[shenki]

https://lists.ozlabs.org/pipermail/openbmc/2016-May/002853.html

[amboar]

@Kenthliu I've replied to @shenki 's review email. In summary, I think we need to configure the debounce in the way that you have in #78, but configuring the directions should be done through skeleton's bin/Barreleye.py or @anoo1 's LED driver.

[Kenthliu]

Yes. For GPIOQ7, I can do that. But for debounce issue, we have to change SCU register to enable. Can Barreleye.py do that?

[amboar]

@Kenthliu personally I'd leave any debounce configuration in the board file. When I've completed the pinctrl driver we can configure it that way. That's a while off though

[Kenthliu]

Both commit fix this issue. It can be closed.
4dbfab2
openbmc/skeleton@584747e