[MLAS] Document SDE based validation of the ISA dispatch tiers - #29903
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hariharans29 merged 2 commits intoJul 28, 2026
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MLAS picks kernels from CPUID at runtime, so a green test suite only covers the tiers the executing machine reaches; several tiers have no covering machine in CI (microsoft#29862). Documents the Intel SDE workflow for exercising a chosen tier, the chip flag to dispatch tier mapping, and the instruction histogram method that distinguishes the ISA kernel actually executing from the fallback passing in its place, including the dynamic versus static section pitfall and the no chip flag trap.
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@hariharans29 Please take a look at your convenience. Thanks |
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Pull request overview
Documents a reproducible developer workflow for validating MLAS runtime CPUID-dispatched ISA tiers (including those not reachable on common CI hardware) using Intel SDE, and links that guidance from the MLAS README to improve discoverability.
Changes:
- Add a new guide (
docs/MLAS_ISA_Validation.md) describing how to run MLAS unit tests under Intel SDE per “chip” target and verify actual kernel execution via-mixinstruction histograms. - Link the new guide from the MLAS README testing section to highlight the limitations of hardware-only validation for dispatched tiers.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| onnxruntime/core/mlas/README.md | Adds a pointer to the new SDE-based validation guide from the MLAS unit test documentation. |
| docs/MLAS_ISA_Validation.md | New documentation describing tier selection with SDE chip flags and verification via instruction histograms. |
hariharans29
previously approved these changes
Jul 27, 2026
hariharans29
enabled auto-merge (squash)
July 27, 2026 22:39
hariharans29
approved these changes
Jul 27, 2026
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Description
Adds
docs/MLAS_ISA_Validation.md: how to exercise a chosen MLAS dispatch tier with Intel SDE (chip flag to tier mapping), and how to prove the ISA kernel actually executed rather than the fallback passing in its place, using the instruction histogram (-mix) with its two pitfalls spelled out (the$static-countssections count unexecuted disassembly, and running with no chip flag exposes every feature rather than a native baseline). Links from the MLAS README's testing section.Motivation and Context
#29862 measured that several dispatch tiers (the AVX-VNNI-INT8 int8 GEMMs, the AMX U8S8 path, the AVX-NE-CONVERT cast) pass the suite identically whether or not the ISA kernel ran, and no current CI machine reaches them. This writes down the manual workflow so it is reproducible by anyone; the pipeline-job half of that issue's proposal is unchanged and separate.