Add HSP clock and reset#28
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dongxuyangeswincomputing wants to merge 8 commits intoeswincomputing:dev/test-upstream-v6.19from
Open
Add HSP clock and reset#28dongxuyangeswincomputing wants to merge 8 commits intoeswincomputing:dev/test-upstream-v6.19from
dongxuyangeswincomputing wants to merge 8 commits intoeswincomputing:dev/test-upstream-v6.19from
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Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add the devres variant of clk_hw_register_divider_parent_data() for registering a divider clock with parent clk data instead of parent name. Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add myself as maintainer of ESWIN EIC7700 clock driver Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add bindings for the high-speed peripherals clock and reset generator on the ESWIN EIC7700 HSP. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add driver for the ESWIN EIC7700 high-speed peripherals system clock controller and register an auxiliary device for system reset controller which is named as "hsp-reset". Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add auxiliary driver to support ESWIN EIC7700 high-speed peripherals system. The reset controller is created using the auxiliary device framework and set up in the clock driver. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add HSP clock and reset generator for EIC7700 SoCs. Update the files for EIC7700 CLOCK DRIVER section. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
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This PR depends on Add clock driver for eic7700 #25