Dev/test upstream v6.18 rc6#18
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linmineswincomputing wants to merge 9 commits intoeswincomputing:dev/test-upstream-v6.18-rc6from
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Dev/test upstream v6.18 rc6#18linmineswincomputing wants to merge 9 commits intoeswincomputing:dev/test-upstream-v6.18-rc6from
linmineswincomputing wants to merge 9 commits intoeswincomputing:dev/test-upstream-v6.18-rc6from
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1.Accessing the High-Speed registers requires the AXI clock to be enabled. 2.This DWC MSHC has a 128MB limitation where the data buffer size and start address must not exceed the 128MB boundary. Registering the missing 'adma_write_desc' callback function. Signed-off-by: Huan He <hehuan1@eswincomputing.com>
The second Ethernet controller (eth1) on the EIC7700 SoC may experience RX data sampling issues at high speed due to EIC7700-specific receive clock to data skew at the MAC input. Add vendor-specific device tree properties to describe optional receive and transmit clock inversion controls used to compensate for the EIC7700 Ethernet MAC, which may be required to ensure correct RX sampling at high speed. This binding also updates the enum values of the rx-internal-delay-ps and tx-internal-delay-ps properties to reflect the actual delay step resolution implemented by the EIC7700 hardware. The hardware applies delay in 20 ps increments, while the previous enum values were based on an incorrect mapping. This change corrects the DT-to-hardware mapping without changing the meaning of the delay properties. In addition, the binding also describes the relevant HSP CSR registers accessed by the MAC. The TXD and RXD delay control registers are included so the driver can explicitly clear any residual configuration left by the bootloader, ensuring the hardware is initialized into a known and deterministic state. Fixes: 888bd0e ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC") Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
…RX sampling timing The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail to sample RX data correctly at Gigabit speed due to EIC7700-specific receive clock to data skew at the MAC input. The existing internal delay configuration does not provide sufficient adjustment range to compensate for this condition. Update the EIC7700 DWMAC glue driver to optionally apply EIC7700-specific clock sampling inversion for Gigabit operation. TXD and RXD delay registers are explicitly cleared during initialization to override any residual configuration left by the bootloader. All HSP CSR register accesses are performed only after the required clocks are enabled. Fixes: ea77dbb ("net: stmmac: add Eswin EIC7700 glue driver") Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Signed-off-by: Min Lin <linmin@eswincomputing.com>
This reverts commit 5e8c3c1.
This reverts commit 2607598.
Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Add myself as maintainer of ESWIN EIC7700 clock driver Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
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