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SVE: Add Z register aliases#95129

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kunalspathak wants to merge 1 commit intodotnet:mainfrom
kunalspathak:z-reg-alias
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SVE: Add Z register aliases#95129
kunalspathak wants to merge 1 commit intodotnet:mainfrom
kunalspathak:z-reg-alias

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@kunalspathak
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Contributes to #94549

@ghost ghost assigned kunalspathak Nov 22, 2023
@kunalspathak kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Nov 22, 2023
@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 22, 2023
@kunalspathak
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@a74nh @dotnet/jit-contrib

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ghost commented Nov 22, 2023

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Issue Details

Contributes to #94549

Author: kunalspathak
Assignees: kunalspathak
Labels:

area-CodeGen-coreclr, arch-arm64-sve

Milestone: -

@a74nh
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a74nh commented Nov 22, 2023

LGTM.

@BruceForstall
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Is this going to be more useful than confusing? I guess the Arm manual itself distinguishes V and Z registers, which seems odd, since V registers are also named Q, D, S, H, and B depending on size, and Z registers contain V registers.

It seems like this won't be helpful because you'll be able to use V instead of Z and vice-versa in the code, and there will be no checking.

@kunalspathak
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It seems like this won't be helpful because you'll be able to use V instead of Z and vice-versa in the code, and there will be no checking.

Sure, V and Z are same registers, but I think while reading code, it will be helpful to know if the instruction operates on scalable "Z" register or a fixed-width "V" register specially around instructions that operates on both Z and V registers.

-theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V0, REG_V0, REG_P0, INS_OPTS_SCALABLE_B);  // IF_SVE_AG_3A /* ANDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb> */
+theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V0, REG_Z0, REG_P0, INS_OPTS_SCALABLE_B);  // IF_SVE_AG_3A /* ANDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb> */

To that matter, I don't think we use REG_V* explicitely anyway apart from unit test and few other places like unwind, where we can continue to use REG_V*.

@BruceForstall
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I think while reading code, it will be helpful to know if the instruction operates on scalable "Z" register or a fixed-width "V" register specially around instructions that operates on both Z and V registers.

The problem is, if there is no correctness checking, then it's not going to be too useful, IMO.

@kunalspathak
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To that matter, I don't think we use REG_V* explicitely anyway apart from unit test and few other places like unwind, where we can continue to use REG_V*.

Taking account of that and @BruceForstall POV, I will close this PR then.

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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI arm-sve Work related to arm64 SVE/SVE2 support

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3 participants