[arm64] Emit cmlt/cmle/fcmlt/fcmle for compares against zero

[AndyAyersMS]

Contain a zero vector operand for CompareLessThan / CompareLessThanOrEqual
so the JIT emits the "less than [or equal to] zero" instruction forms
(cmlt, cmle, fcmlt, fcmle) instead of materializing a zero vector and
swapping the operands.

Before:

movi v16.4s, #0
cmgt v0.4s, v16.4s, v0.4s

After:

cmlt v0.4s, v0.4s, #0

These instructions were defined in the emitter but never selected in real
codegen. This mirrors the existing containment for CompareGreaterThan /
CompareGreaterThanOrEqual / CompareEqual. Unsigned base types are excluded
since the cmlt/cmle "with zero" forms are signed-only.

Codegen-check coverage is added to the existing Runtime_33972 test for the
vector and scalar int32/int64/float/double cases.

Fixes #64785.

Note

This pull request was generated with the assistance of GitHub Copilot.

[AndyAyersMS]

@dhartglassMSFT PTAL

(I'm just scanning for "old, neglected" arm64 cq issues)

[Copilot]

Pull request overview

This PR updates ARM64 HWIntrinsic lowering/codegen so AdvSimd.CompareLessThan* and CompareLessThanOrEqual* against a zero vector can be represented with a contained zero operand and emitted using the dedicated “compare vs zero” instruction forms (cmlt, cmle, fcmlt, fcmle) rather than materializing a zero vector and swapping operands.

Changes:

• Add containment support for CompareLessThan* / CompareLessThanOrEqual* when op2 is a zero vector (excluding unsigned base types).
• Teach ARM64 HWIntrinsic codegen to select cmlt/cmle/fcmlt/fcmle when the second operand is a contained zero.
• Extend the existing Runtime_33972 JIT regression test with ARM64 codegen-check coverage and runtime validation for representative vector and scalar cases.

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated no comments.

File	Description
src/coreclr/jit/lowerarmarch.cpp	Adds containment for zero op2 on less-than / less-than-or-equal AdvSimd intrinsics (signed-only).
src/coreclr/jit/hwintrinsiclistarm64.h	Marks the relevant intrinsics as supporting containment / constant-prop to enable the new lowering path.
src/coreclr/jit/hwintrinsiccodegenarm64.cpp	Emits cmlt/cmle/fcmlt/fcmle when op2 is a contained zero; otherwise preserves the prior operand-swap emission.
src/tests/JIT/Regression/JitBlue/Runtime_33972/Runtime_33972.cs	Adds codegen-check assertions and functional validation for the new zero-compare instruction selection.

[dhartglassMSFT]

Nit, could add a testcase for

• CompareLessthan Vector128 with signed-byte types
• A negative test for CompareLessthan with an unsigned type, since lowering has that extra check in it

(I'm not able to "at-copilot" for this PR)

[AndyAyersMS]

Good call — added both in 6b0511d:

• AdvSimd_CompareLessThan_Vector128_SByte_Zero (checks cmlt v0.16b, v0.16b, #0)
• AdvSimd_CompareLessThan_Vector128_Byte_Zero, an ARM64-NOT: cmlt negative test for the unsigned path (it stays uncontained and folds to movi #0, since unsigned < 0 is always false).

Both pass locally. Mind re-approving when you get a chance?

Note

This reply was generated with the assistance of GitHub Copilot.

[dhartglassMSFT]

Change LGTM aside from extra test or two we might want.