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Add SHA3 and SVE SHA3 APIs #126941

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c84f28a
Add SHA3 and SVE SHA3 APIs
a74nh Feb 6, 2026
6aba4ae
Remove semicolon
a74nh Apr 20, 2026
a82a586
remove unsafe
a74nh Apr 20, 2026
755e33a
Merge branch 'main' into sha3_github
dhartglassMSFT May 1, 2026
3e1cd66
Fix Sha3.cs typos
a74nh May 11, 2026
de44a1f
Add header
a74nh May 11, 2026
069f472
Merge branch 'main' into sha3_github
a74nh May 26, 2026
df43596
Merge branch 'main' into sha3_github
dhartglassMSFT Jun 15, 2026
ade015e
change simd sizes to 16
a74nh Jun 17, 2026
067c8a8
Use SVE instruction
a74nh Jun 17, 2026
172c067
Fix PlatformNotSupported files
a74nh Jun 17, 2026
48926be
Remove unused using
a74nh Jun 17, 2026
9acdeed
Add header
a74nh Jun 17, 2026
8bae42b
Add special codegen for NI_SveSha3_BitwiseRotateLeftBy1AndXor
a74nh Jun 17, 2026
42a9176
fix SveSha3 cs files
a74nh Jun 17, 2026
92e3c1f
Add CompatibilitySuppressions
a74nh Jun 18, 2026
2dc2f8e
Revert "Add CompatibilitySuppressions"
a74nh Jun 18, 2026
9f0c755
Add SYSLIB5003 to intrinsics
a74nh Jun 18, 2026
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4 changes: 2 additions & 2 deletions src/coreclr/jit/hwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1011,10 +1011,10 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // Rcpc2
{ FIRST_NI_Sve, LAST_NI_Sve }, // Sve
{ FIRST_NI_Sve2, LAST_NI_Sve2 }, // Sve2
{ NI_Illegal, NI_Illegal }, // Sha3
{ FIRST_NI_Sha3, LAST_NI_Sha3 }, // Sha3
{ NI_Illegal, NI_Illegal }, // Sm4
{ NI_Illegal, NI_Illegal }, // SveAes
{ NI_Illegal, NI_Illegal }, // SveSha3
{ FIRST_NI_SveSha3, LAST_NI_SveSha3 }, // SveSha3
{ NI_Illegal, NI_Illegal }, // SveSm4
{ FIRST_NI_ArmBase_Arm64, LAST_NI_ArmBase_Arm64 }, // ArmBase_Arm64
{ FIRST_NI_AdvSimd_Arm64, LAST_NI_AdvSimd_Arm64 }, // AdvSimd_Arm64
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5 changes: 5 additions & 0 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -576,6 +576,11 @@ void HWIntrinsicInfo::lookupImmBounds(
immUpperBound = 7;
break;

case NI_Sha3_XorRotateRight:
immLowerBound = 0;
immUpperBound = 63;
break;

default:
unreached();
}
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28 changes: 26 additions & 2 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -1239,9 +1239,21 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;

case 3:
assert(!hasImmediateOperand);

GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt);
if (hasImmediateOperand)
{
assert(!isRMW);
HWIntrinsicImmOpHelper helper(this, intrin.op3, node);
for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const int imm = helper.ImmValue();
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, imm, opt);
}
}
else
{
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt);
}
break;

default:
Expand Down Expand Up @@ -2116,6 +2128,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg);
break;

case NI_Sha3_BitwiseClearXor:
case NI_Sha3_Xor:
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, INS_OPTS_16B);
break;

case NI_Sve_ConvertMaskToVector:
// PMOV would be ideal here, but it is in SVE2.1.
// Instead, use a predicated move: MOV <Zd>.<T>, <Pg>/Z, #1
Expand Down Expand Up @@ -3110,6 +3127,13 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_SveSha3_BitwiseRotateLeftBy1AndXor:
{
opt = INS_OPTS_SCALABLE_D;
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
break;
}

default:
unreached();
}
Expand Down
13 changes: 13 additions & 0 deletions src/coreclr/jit/hwintrinsiclistarm64.h
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Expand Up @@ -875,6 +875,19 @@ HARDWARE_INTRINSIC(Sha256, ScheduleUpdate0,
HARDWARE_INTRINSIC(Sha256, ScheduleUpdate1, 16, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sha256su1, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasRMWSemantics)
#define LAST_NI_Sha256 NI_Sha256_ScheduleUpdate1

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// Sha3
#define FIRST_NI_Sha3 NI_Sha3_BitwiseClearXor
HARDWARE_INTRINSIC(Sha3, BitwiseClearXor, 16, 3, {INS_bcax, INS_bcax, INS_bcax, INS_bcax, INS_bcax, INS_bcax, INS_bcax, INS_bcax, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sha3, BitwiseRotateLeftBy1AndXor, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rax1, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(Sha3, Xor, 16, 3, {INS_eor3, INS_eor3, INS_eor3, INS_eor3, INS_eor3, INS_eor3, INS_eor3, INS_eor3, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sha3, XorRotateRight, 16, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_xar, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_HasImmediateOperand)
#define LAST_NI_Sha3 NI_Sha3_XorRotateRight


#endif // FEATURE_HW_INTRINSIC

#include "hwintrinsiclistarm64sve.h"
Expand Down
9 changes: 9 additions & 0 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
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Original file line number Diff line number Diff line change
Expand Up @@ -519,6 +519,15 @@ HARDWARE_INTRINSIC(Sve2, Xor,
HARDWARE_INTRINSIC(Sve2, XorRotateRight, -1, 3, {INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasRMWSemantics|HW_Flag_HasImmediateOperand)
#define LAST_NI_Sve2 NI_Sve2_XorRotateRight

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// Sha3
#define FIRST_NI_SveSha3 NI_SveSha3_BitwiseRotateLeftBy1AndXor
HARDWARE_INTRINSIC(SveSha3, BitwiseRotateLeftBy1AndXor, -1, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rax1, INS_sve_rax1, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SpecialCodeGen)
#define LAST_NI_SveSha3 NI_SveSha3_BitwiseRotateLeftBy1AndXor
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// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
Expand Down
9 changes: 9 additions & 0 deletions src/coreclr/jit/lowerarmarch.cpp
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Expand Up @@ -4053,6 +4053,15 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;

case NI_Sha3_XorRotateRight:
assert(hasImmediateOperand);
assert(varTypeIsIntegral(intrin.op3));
if (intrin.op3->IsCnsIntOrI())
{
MakeSrcContained(node, intrin.op3);
}
break;

default:
unreached();
}
Expand Down
11 changes: 3 additions & 8 deletions src/coreclr/jit/lsraarm64.cpp
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Expand Up @@ -1690,13 +1690,16 @@ void LinearScan::BuildHWIntrinsicImmediate(GenTreeHWIntrinsic* intrinsicTree, co
case NI_AdvSimd_Arm64_LoadAndInsertScalarVector128x3:
case NI_AdvSimd_Arm64_LoadAndInsertScalarVector128x4:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
case NI_Sve_ShiftRightArithmeticForDivide:
needBranchTargetReg = !intrin.op2->isContainedIntOrIImmed();
break;

case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_StoreSelectedScalar:
case NI_Sha3_XorRotateRight:
case NI_Sve_AddRotateComplex:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
Expand Down Expand Up @@ -1782,14 +1785,6 @@ void LinearScan::BuildHWIntrinsicImmediate(GenTreeHWIntrinsic* intrinsicTree, co
setInternalRegsDelayFree = true;
break;

case NI_Sve_ShiftRightArithmeticForDivide:
needBranchTargetReg = !intrin.op2->isContainedIntOrIImmed();
break;

case NI_Sve_AddRotateComplex:
needBranchTargetReg = !intrin.op3->isContainedIntOrIImmed();
break;

case NI_Sve_MultiplyAddRotateComplex:
case NI_Sve2_MultiplyAddRotateComplex:
case NI_Sve2_MultiplyAddRoundedDoublingSaturateHighRotateComplex:
Expand Down
12 changes: 12 additions & 0 deletions src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml
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Expand Up @@ -63,5 +63,17 @@
<type fullname="System.Runtime.Intrinsics.Arm.Sve2/Arm64">
<method signature="System.Boolean get_IsSupported()" body="stub" value="false" />
</type>
<type fullname="System.Runtime.Intrinsics.Arm.Sha3">
<method signature="System.Boolean get_IsSupported()" body="stub" value="false" />
</type>
<type fullname="System.Runtime.Intrinsics.Arm.Sha3/Arm64">
<method signature="System.Boolean get_IsSupported()" body="stub" value="false" />
</type>
<type fullname="System.Runtime.Intrinsics.Arm.SveSha3">
<method signature="System.Boolean get_IsSupported()" body="stub" value="false" />
</type>
<type fullname="System.Runtime.Intrinsics.Arm.SveSha3/Arm64">
<method signature="System.Boolean get_IsSupported()" body="stub" value="false" />
</type>
</assembly>
</linker>
4 changes: 4 additions & 0 deletions src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems
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Expand Up @@ -2867,6 +2867,8 @@
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sha256.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sve.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sve2.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sha3.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\SveSha3.cs" />
</ItemGroup>
<ItemGroup Condition="'$(SupportsArmIntrinsics)' != 'true'">
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\AdvSimd.PlatformNotSupported.cs" />
Expand All @@ -2879,6 +2881,8 @@
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sha256.PlatformNotSupported.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sve.PlatformNotSupported.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sve2.PlatformNotSupported.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\Sha3.PlatformNotSupported.cs" />
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Arm\SveSha3.PlatformNotSupported.cs" />
</ItemGroup>
<ItemGroup Condition="'$(SupportsWasmIntrinsics)' == 'true'">
<Compile Include="$(MSBuildThisFileDirectory)System\Runtime\Intrinsics\Wasm\WasmBase.cs" />
Expand Down
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