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[RISC-V] Replace addi, addiw with mov, sext.w when immediate is zero#117932

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jakobbotsch merged 2 commits intodotnet:mainfrom
vmolab:refactor_inst
Aug 6, 2025
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[RISC-V] Replace addi, addiw with mov, sext.w when immediate is zero#117932
jakobbotsch merged 2 commits intodotnet:mainfrom
vmolab:refactor_inst

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@credo-quia-absurdum credo-quia-absurdum commented Jul 22, 2025

Replace addi, addiw with mov, sext.w when immediate is zero

@clamp03 @tomeksowi @SkyShield, @namu-lee
part of #84834, cc @dotnet/samsung

Copilot AI review requested due to automatic review settings July 22, 2025 14:27
Copilot AI reviewed Jul 22, 2025
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Pull Request Overview

This PR optimizes RISC-V assembly code generation by replacing addi/addiw instructions with more appropriate mov/sext.w instructions when the immediate value is zero. This change improves code clarity and potentially performance by using semantically correct instructions for register moves and sign extension operations.

Key changes:

  • Replace addi rd, rs, 0 with mov rd, rs for 64-bit register moves
  • Replace addiw rd, rs, 0 with sext.w rd, rs for 32-bit sign extension operations
  • Update conditional logic to use appropriate instruction based on attribute size

@github-actions github-actions bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jul 22, 2025
@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Jul 22, 2025
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dotnet-policy-service bot commented Jul 22, 2025

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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@build-analysis build-analysis bot mentioned this pull request Jul 22, 2025
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@clamp03 clamp03 added the arch-riscv Related to the RISC-V architecture label Jul 23, 2025
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sirntar commented Jul 25, 2025

@risc-vv /run

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risc-vv commented Jul 25, 2025 •
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RISC-V Release-CLR-QEMU: 9092 / 9122 (99.67%) 
=======================
      passed: 9092
      failed: 2
     skipped: 596
      killed: 28
------------------------
 TOTAL tests: 9718
VIRTUAL time: 37h 32min 19s 65ms
   REAL time: 38min 17s 563ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 284268 / 285403 (99.60%) 
=======================
      passed: 284268
      failed: 1127
     skipped: 39
      killed: 8
------------------------
 TOTAL tests: 285442
VIRTUAL time: 33h 16min 25s 178ms
   REAL time: 1h 12min 37s 570ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-VF2: 9093 / 9123 (99.67%) 
=======================
      passed: 9093
      failed: 2
     skipped: 596
      killed: 28
------------------------
 TOTAL tests: 9719
VIRTUAL time: 11h 56min 43s 238ms
   REAL time: 48min 15s 33ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 307796 / 309263 (99.53%) 
=======================
      passed: 307796
      failed: 1459
     skipped: 39
      killed: 8
------------------------
 TOTAL tests: 309302
VIRTUAL time: 21h 41min 2s 301ms
   REAL time: 2h 19min 50s 28ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 3d45d1687dda1fe42a7e2d79403c8de986144dda
CI: 785da59dadeb491bca87651db4b40a68883f8a00
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

@clamp03 clamp03 requested a review from jakobbotsch July 28, 2025 04:52
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clamp03 commented Jul 31, 2025

@jakobbotsch Could you review this PR and #117967 as well? Thank you.

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clamp03 commented Aug 5, 2025

@jakobbotsch Could you review this PR too? Thank you.

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jakobbotsch commented Aug 5, 2025

/ba-g Unknown failure was #117961

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jakobbotsch commented Aug 6, 2025

/ba-g Unknown failure was #117961

@jakobbotsch jakobbotsch merged commit 82f0bd1 into dotnet:main Aug 6, 2025
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@jakobbotsch jakobbotsch jakobbotsch approved these changes

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@tomeksowi tomeksowi tomeksowi approved these changes

@clamp03 clamp03 clamp03 approved these changes

@sirntar sirntar sirntar approved these changes

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arch-riscv Related to the RISC-V architecture area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI community-contribution Indicates that the PR has been added by a community member

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