JIT arm32: Assertion failed 'refPosition->RegOptional()' in 'System.Numerics.Tests.ComplexTests:Abs(double,double)' during 'LSRA build intervals' when using non-standard arg sort

[jakobbotsch]

1. Comment the code in CallArgs::SortArgs that does the sort (everything after the initial loop that assigns sortedArgs)
2. Run superpmi replay over arm32 with COMPlus_JitStressRegs=3

Result:

[22:19:58] ISSUE: <ASSERT> #271154 D:\a\_work\1\s\src\coreclr\jit\lsra.cpp (11934) - Assertion failed 'refPosition->RegOptional()' in 'System.Numerics.Tests.ComplexTests:Abs(double,double)' during 'LSRA build intervals' (IL size 22; hash 0xbf3bc3d1; FullOpts)

category:correctness
theme:register-allocator

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Issue Details

---

1. Comment the code in CallArgs::SortArgs that does the sort (everything after the initial loop that assigns sortedArgs)
2. Run superpmi replay over arm32

Result:

[22:19:58] ISSUE: <ASSERT> #271154 D:\a\_work\1\s\src\coreclr\jit\lsra.cpp (11934) - Assertion failed 'refPosition->RegOptional()' in 'System.Numerics.Tests.ComplexTests:Abs(double,double)' during 'LSRA build intervals' (IL size 22; hash 0xbf3bc3d1; FullOpts)

Author:	jakobbotsch
Assignees:	-
Labels:	area-CodeGen-coreclr, untriaged
Milestone:	-

[JulieLeeMSFT]

cc @BruceForstall @kunalspathak

seems like a bug in either lowering or LSRA

[kunalspathak]

Do we know why this is 7.0 and not 8.0?

[kunalspathak]

@jakobbotsch - I just tried on main and I do not repro it. Can you confirm the exact .mc file that I can try?

[jakobbotsch]

@kunalspathak The superpmi-replay run that failed was this one: https://dev.azure.com/dnceng-public/public/_build/results?buildId=32422&view=results

Looks like it also needs COMPlus_JitStressRegs=3. Sorry about that, didn't realize superpmi-replay runs with stress modes also.

[kunalspathak]

needs COMPlus_JitStressRegs=3

Yes, was able to repro with that.

superpmi-replay runs with stress modes also.

Yes, it runs with all the JitStressRegs switches because replay doesn't complain about missing contexts for them, and the collection is still valid, unlike with JitStress.

Perhaps it would be too early for me to comment on this given the limited knowledge I have around PutArg. I will spend some more time to see why we hit into it. But essentially, we are not able to find a free pair of registers to allocate because they are either occupied or marked as "busy until next kill". In such case, we expect at least the ref position to be marked as "RegOptional()", but that's not the case either, which I am not sure should be the right thing to do or there is other problem somewhere else.

─────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤
LocRP# Name Type  Action    Reg  │r0  │r1  │r2  │r3  │r4  │r5  │f0  │f1  │f2  │f3  │f16 │f17 │
─────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤
 0.#1  V1   Parm   Keep     f2   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
 1.#2  BB1 PredBB0               │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
 7.#3  f0   Fixd   Keep     f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
 7.#4  V0   Use    Keep     f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
 8.#5  f0   Fixd   Keep     f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
 8.#6  I2   Def    PtArg    f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
11.#7  f2   Fixd   Keep     f2   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
11.#8  V1   Use    Keep     f2   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
12.#9  f2   Fixd   Keep     f2   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
12.#10 I3   Def    PtArg    f2   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
17.#11 V0   Use    Keep     f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
17.#12 V0   Use *  Keep     f0   │    │    │    │    │    │    │V0 a│V0 a│V1 a│V1 a│    │    │
18.#13 I4   Def    Alloc    f16  │    │    │    │    │    │    │Busy│Busy│V1 a│V1 a│I4 a│I4 a│
23.#14 V1   Use    Keep     f2   │    │    │    │    │    │    │Busy│Busy│V1 a│V1 a│I4 a│I4 a│
23.#15 V1   Use *  Keep     f2   │    │    │    │    │    │    │Busy│Busy│V1 a│V1 a│I4 a│I4 a│
24.#16 I5   Def    Spill    f16  │    │    │    │    │    │    │Busy│Busy│Busy│Busy│    │    │
                   Alloc    f16  │    │    │    │    │    │    │Busy│Busy│Busy│Busy│I5 a│I5 a│
25.#17 I4   Use *  ReLod    NA   │    │    │    │    │    │    │Busy│Busy│Busy│Busy│I5 a│I5 a│
                   Spill    f16  │    │    │    │    │    │    │Busy│Busy│Busy│Busy│    │    │
                   Alloc    f16  │    │    │    │    │    │    │Busy│Busy│Busy│Busy│I4 a│I4 a│
25.#18 I5   Use *  ReLod    NA   │    │    │    │    │    │    │Busy│Busy│Busy│Busy│I4 a│I4 a│

[jakobbotsch]

What does the IR around this call look like? It's possible the IR produced around the PUTARGs is also wrong (in particular, upstream should ensure we don't see calls with overlapping arg placement).