AArch64 LSE atomic_rmw support#3322
Conversation
|
It'd be a good idea add a |
|
Currently we force QEMU to emulate a processor that lacks LSE support. |
|
I was curious if QEMU has any |
|
(This was added 9 days ago so I expect we'd have to pull down a git checkout of qemu rather than build a release; but that's probably fine IMHO.) |
What might be a more scalable, though less pretty option, would be to use the max configuration and turn off the features that we don't want (only PAC?) @akirilov-arm is working on that feature currently so I imagine we'd need testing at some point in the near future. But I haven't ever had to disable features with QEMU, and briefly looking at the code, I'm wondering if all the features have a nice user facing option... |
|
Reading this, it looks like we can just |
53d44e8 to
71b3533
Compare
Rename the existing AtomicRMW to AtomicRMWLoop and directly lower atomic_rmw operations, without a loop if LSE support is available. Copyright (c) 2021, Arm Limited
71b3533 to
62a3177
Compare
|
As a side note, this is somewhat unlikely to get used much in practice at least with Wasmtime itself due to this block which is gated on the off-by-default |
|
Yes, we are aware of that - my colleague @adamgemmell from Arm's Rust team has proposed stabilising the ISA extension test macro in issue rust-lang/rust#86941 independently of the |
|
Nice! And yeah of course I think this is fine to land (as well as any other improvements). Just because Wasmtime doesn't use something by default doesn't mean it's not useful! |
|
@cfallin, would you be able to look at this now the QEMU changes have landed? |
Rename the existing AtomicRMW to AtomicRMWLoop and directly lower
atomic_rmw operations, without a loop if LSE support is available.
Copyright (c) 2021, Arm Limited