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make arm-v6/7/8m compatible with signal delivery inside irq handler #15048

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Merged
xiaoxiang781216 merged 5 commits into from
Dec 5, 2024
Merged

make arm-v6/7/8m compatible with signal delivery inside irq handler #15048

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e713f54
arm-v6/7/8m: sigaction should use running_task
jasonbu Dec 4, 2024
0f262b9
arm-v6/7/8m: sigaction forward to pendsv
jasonbu Dec 4, 2024
8d0bd7b
Revert "arm/cxd56: use chip specific vectors to allow smpcall update …
jasonbu Dec 4, 2024
f5b43c7
Revert "arm/lc823450: use custom vectors to make smp_call work with e…
jasonbu Dec 4, 2024
99fb05c
Revert "arm/rp2040: use custom vectors to make smp_call work with exc…
jasonbu Dec 4, 2024
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3 changes: 0 additions & 3 deletions arch/arm/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -223,7 +223,6 @@ config ARCH_CHIP_LC823450
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_HAVE_CUSTOM_VECTORS
---help---
ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)

Expand Down Expand Up @@ -351,7 +350,6 @@ config ARCH_CHIP_RP2040
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_BOARD_COMMON
select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_HAVE_CUSTOM_VECTORS
---help---
Raspberry Pi RP2040 architectures (ARM dual Cortex-M0+).

Expand Down Expand Up @@ -687,7 +685,6 @@ config ARCH_CHIP_CXD56XX
select ARCH_HAVE_MATH_H
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_HAVE_CUSTOM_VECTORS
select LIBC_ARCH_ATOMIC if SMP
---help---
Sony CXD56XX (ARM Cortex-M4) architectures
Expand Down
10 changes: 8 additions & 2 deletions arch/arm/src/armv6-m/arm_doirq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,15 +57,15 @@ void exception_direct(void)
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
struct tcb_s **running_task = &g_running_tasks[this_cpu()];
FAR struct tcb_s *tcb;
struct tcb_s *tcb = *running_task;

/* This judgment proves that (*running_task)->xcp.regs
* is invalid, and we can safely overwrite it.
*/

if (!(NVIC_IRQ_SVCALL == irq && regs[REG_R0] == SYS_restore_context))
{
(*running_task)->xcp.regs = regs;
tcb->xcp.regs = regs;
}

board_autoled_on(LED_INIRQ);
Expand All @@ -84,6 +84,12 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)

irq_dispatch(irq, regs);
#endif
if (tcb->sigdeliver)
{
/* Pendsv able to access running tcb with no critical section */

up_schedule_sigaction(tcb);
}

up_irq_save();
}
Expand Down
17 changes: 13 additions & 4 deletions arch/arm/src/armv6-m/arm_schedulesigaction.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
#include "sched/sched.h"
#include "arm_internal.h"
#include "irq/irq.h"
#include "nvic.h"

/****************************************************************************
* Public Functions
Expand Down Expand Up @@ -80,14 +81,14 @@

void up_schedule_sigaction(struct tcb_s *tcb)
{
sinfo("tcb=%p, rtcb=%p current_regs=%p\n", tcb, this_task(),
this_task()->xcp.regs);
struct tcb_s *rtcb = running_task();
uint32_t ipsr = getipsr();

/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/

if (tcb == this_task() && !up_interrupt_context())
if (tcb == rtcb && ipsr == 0)
{
/* In this case just deliver the signal now.
* REVISIT: Signal handle will run in a critical section!
Expand All @@ -96,7 +97,15 @@ void up_schedule_sigaction(struct tcb_s *tcb)
(tcb->sigdeliver)(tcb);
tcb->sigdeliver = NULL;
}
else
else if (tcb == rtcb && ipsr != NVIC_IRQ_PENDSV)
{
/* Context switch should be done in pendsv, for exception directly
* last regs is not saved tcb->xcp.regs.
*/

up_trigger_irq(NVIC_IRQ_PENDSV, 0);
}
else /* ipsr == NVIC_IRQ_PENDSV || tcb != rtcb */
{
/* Save the return PC, CPSR and either the BASEPRI or PRIMASK
* registers (and perhaps also the LR). These will be restored
Expand Down
10 changes: 8 additions & 2 deletions arch/arm/src/armv7-m/arm_doirq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,15 +57,15 @@ void exception_direct(void)
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
struct tcb_s **running_task = &g_running_tasks[this_cpu()];
FAR struct tcb_s *tcb;
struct tcb_s *tcb = *running_task;

/* This judgment proves that (*running_task)->xcp.regs
* is invalid, and we can safely overwrite it.
*/

if (!(NVIC_IRQ_SVCALL == irq && regs[REG_R0] == SYS_restore_context))
{
(*running_task)->xcp.regs = regs;
tcb->xcp.regs = regs;
}

board_autoled_on(LED_INIRQ);
Expand All @@ -84,6 +84,12 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)

irq_dispatch(irq, regs);
#endif
if (tcb->sigdeliver)
{
/* Pendsv able to access running tcb with no critical section */

up_schedule_sigaction(tcb);
}

up_irq_save();
}
Expand Down
17 changes: 13 additions & 4 deletions arch/arm/src/armv7-m/arm_schedulesigaction.c
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
#include "sched/sched.h"
#include "arm_internal.h"
#include "irq/irq.h"
#include "nvic.h"

/****************************************************************************
* Public Functions
Expand Down Expand Up @@ -81,14 +82,14 @@

void up_schedule_sigaction(struct tcb_s *tcb)
{
sinfo("tcb=%p, rtcb=%p current_regs=%p\n", tcb, this_task(),
this_task()->xcp.regs);
struct tcb_s *rtcb = running_task();
uint32_t ipsr = getipsr();

/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/

if (tcb == this_task() && !up_interrupt_context())
if (tcb == rtcb && ipsr == 0)
{
/* In this case just deliver the signal now.
* REVISIT: Signal handle will run in a critical section!
Expand All @@ -97,7 +98,15 @@ void up_schedule_sigaction(struct tcb_s *tcb)
(tcb->sigdeliver)(tcb);
tcb->sigdeliver = NULL;
}
else
else if (tcb == rtcb && ipsr != NVIC_IRQ_PENDSV)
{
/* Context switch should be done in pendsv, for exception directly
* last regs is not saved tcb->xcp.regs.
Comment thread
jasonbu marked this conversation as resolved.
*/

up_trigger_irq(NVIC_IRQ_PENDSV, 0);
}
else /* ipsr == NVIC_IRQ_PENDSV || tcb != rtcb */
{
/* Save the return PC, CPSR and either the BASEPRI or PRIMASK
* registers (and perhaps also the LR). These will be restored
Expand Down
10 changes: 8 additions & 2 deletions arch/arm/src/armv8-m/arm_doirq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -68,15 +68,15 @@ void exception_direct(void)
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
struct tcb_s **running_task = &g_running_tasks[this_cpu()];
FAR struct tcb_s *tcb;
struct tcb_s *tcb = *running_task;

/* This judgment proves that (*running_task)->xcp.regs
* is invalid, and we can safely overwrite it.
*/

if (!(NVIC_IRQ_SVCALL == irq && regs[REG_R0] == SYS_restore_context))
{
(*running_task)->xcp.regs = regs;
tcb->xcp.regs = regs;
}

board_autoled_on(LED_INIRQ);
Expand All @@ -95,6 +95,12 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)

irq_dispatch(irq, regs);
#endif
if (tcb->sigdeliver)
{
/* Pendsv able to access running tcb with no critical section */

up_schedule_sigaction(tcb);
}

up_irq_save();
}
Expand Down
17 changes: 13 additions & 4 deletions arch/arm/src/armv8-m/arm_schedulesigaction.c
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
#include "sched/sched.h"
#include "arm_internal.h"
#include "irq/irq.h"
#include "nvic.h"

/****************************************************************************
* Public Functions
Expand Down Expand Up @@ -81,14 +82,14 @@

void up_schedule_sigaction(struct tcb_s *tcb)
{
sinfo("tcb=%p, rtcb=%p current_regs=%p\n", tcb, this_task(),
this_task()->xcp.regs);
struct tcb_s *rtcb = running_task();
uint32_t ipsr = getipsr();

/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/

if (tcb == this_task() && !up_interrupt_context())
if (tcb == rtcb && ipsr == 0)
{
/* In this case just deliver the signal now.
* REVISIT: Signal handle will run in a critical section!
Expand All @@ -97,7 +98,15 @@ void up_schedule_sigaction(struct tcb_s *tcb)
(tcb->sigdeliver)(tcb);
tcb->sigdeliver = NULL;
}
else
else if (tcb == rtcb && ipsr != NVIC_IRQ_PENDSV)
{
/* Context switch should be done in pendsv, for exception directly
* last regs is not saved tcb->xcp.regs.
Comment thread
jasonbu marked this conversation as resolved.
*/

up_trigger_irq(NVIC_IRQ_PENDSV, 0);
}
else /* ipsr == NVIC_IRQ_PENDSV || tcb != rtcb */
{
/* Save the return PC, CPSR and either the BASEPRI or PRIMASK
* registers (and perhaps also the LR). These will be restored
Expand Down
3 changes: 1 addition & 2 deletions arch/arm/src/cxd56xx/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,7 @@ set(SRCS
cxd56_icc.c
cxd56_powermgr.c
cxd56_farapi.c
cxd56_sysctl.c
cxd56_vectors.c)
cxd56_sysctl.c)

if(CONFIG_SMP)
list(APPEND SRCS cxd56_cpuidlestack.c)
Expand Down
1 change: 0 additions & 1 deletion arch/arm/src/cxd56xx/Make.defs
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ CHIP_CSRCS += cxd56_icc.c
CHIP_CSRCS += cxd56_powermgr.c
CHIP_CSRCS += cxd56_farapi.c
CHIP_CSRCS += cxd56_sysctl.c
CHIP_CSRCS += cxd56_vectors.c

ifeq ($(CONFIG_SMP), y)
CHIP_CSRCS += cxd56_cpuidlestack.c
Expand Down
107 changes: 0 additions & 107 deletions arch/arm/src/cxd56xx/cxd56_vectors.c
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This file was deleted.

2 changes: 1 addition & 1 deletion arch/arm/src/lc823450/Make.defs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ include armv7-m/Make.defs

CHIP_CSRCS = lc823450_allocateheap2.c lc823450_start.c lc823450_irq.c lc823450_timer.c
CHIP_CSRCS += lc823450_lowputc.c lc823450_serial.c lc823450_clockconfig.c
CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c lc823450_vectors.c
CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c

# Configuration-dependent LC823450 files

Expand Down
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