arm/cortex-a,r: replace cp15 instruct to macros to align operation

arch/arm/src/armv7-a/cp15.h → arch/arm/include/armv7-a/cp15.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/cp15.h
+ * arch/arm/include/armv7-a/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

arch/arm/include/armv7-a/irq.h

@@ -36,6 +36,8 @@
 #  include <stdint.h>
 #endif
 
+#include <arch/armv7-a/cp15.h>
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -457,11 +459,7 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -500,23 +498,13 @@ static inline_function uint32_t up_getsp(void)
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
 }
 
 noinstrument_function

arch/arm/src/armv7-r/cp15.h → arch/arm/include/armv7-r/cp15.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-r/cp15.h
+ * arch/arm/include/armv7-r/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

arch/arm/include/armv7-r/irq.h

@@ -36,6 +36,8 @@
 #  include <stdint.h>
 #endif
 
+#include <arch/armv7-r/cp15.h>
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -357,7 +359,7 @@ static inline irqstate_t irqstate(void)
 
 /* Disable IRQs and return the previous IRQ state */
 
-static inline irqstate_t up_irq_save(void)
+noinstrument_function static inline irqstate_t up_irq_save(void)
 {
   unsigned int cpsr;
 
@@ -417,7 +419,7 @@ static inline irqstate_t up_irq_disable(void)
 
 /* Restore saved IRQ & FIQ state */
 
-static inline void up_irq_restore(irqstate_t flags)
+noinstrument_function static inline void up_irq_restore(irqstate_t flags)
 {
   __asm__ __volatile__
     (
@@ -452,11 +454,7 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -479,26 +477,29 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
+/****************************************************************************
+ * Name:
+ *   up_current_regs/up_set_current_regs
+ *
+ * Description:
+ *   We use the following code to manipulate the TPIDRPRW register,
+ *   which exists uniquely for each CPU and is primarily designed to store
+ *   current thread information. Currently, we leverage it to store interrupt
+ *   information, with plans to further optimize its use for storing both
+ *   thread and interrupt information in the future.
+ *
+ ****************************************************************************/
+
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
 }
 
 noinstrument_function

arch/arm/src/armv8-r/cp15.h → arch/arm/include/armv8-r/cp15.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv8-r/cp15.h
+ * arch/arm/include/armv8-r/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

arch/arm/include/armv8-r/irq.h

@@ -36,6 +36,8 @@
 #  include <stdint.h>
 #endif
 
+#include <arch/armv8-r/cp15.h>
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -357,7 +359,7 @@ static inline irqstate_t irqstate(void)
 
 /* Disable IRQs and return the previous IRQ state */
 
-static inline irqstate_t up_irq_save(void)
+noinstrument_function static inline irqstate_t up_irq_save(void)
 {
   unsigned int cpsr;
 
@@ -417,7 +419,7 @@ static inline irqstate_t up_irq_disable(void)
 
 /* Restore saved IRQ & FIQ state */
 
-static inline void up_irq_restore(irqstate_t flags)
+noinstrument_function static inline void up_irq_restore(irqstate_t flags)
 {
   __asm__ __volatile__
     (
@@ -452,11 +454,7 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -479,26 +477,29 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
+/****************************************************************************
+ * Name:
+ *   up_current_regs/up_set_current_regs
+ *
+ * Description:
+ *   We use the following code to manipulate the TPIDRPRW register,
+ *   which exists uniquely for each CPU and is primarily designed to store
+ *   current thread information. Currently, we leverage it to store interrupt
+ *   information, with plans to further optimize its use for storing both
+ *   thread and interrupt information in the future.
+ *
+ ****************************************************************************/
+
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
 }
 
 noinstrument_function

arch/arm/src/armv7-a/arm_cpuhead.S

@@ -27,7 +27,6 @@
 #include <arch/irq.h>
 
 #include "arm.h"
-#include "cp15.h"
 #include "sctlr.h"
 #include "mmu.h"
 #include "smp.h"

arch/arm/src/armv7-a/arm_cpuinfo.c

@@ -26,9 +26,10 @@
 #include <nuttx/config.h>
 #include <nuttx/fs/procfs.h>
 
+#include <arch/irq.h>
+
 #include "arm_internal.h"
 #include "hwcap.h"
-#include "cp15.h"
 
 #if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_CPUINFO)
 

arch/arm/src/armv7-a/arm_fpuconfig.S

@@ -23,7 +23,8 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include "cp15.h"
+
+#include <arch/irq.h>
 
 #ifdef CONFIG_ARCH_FPU
 

arch/arm/src/armv7-a/arm_head.S

@@ -24,8 +24,9 @@
 
 #include <nuttx/config.h>
 
+#include <arch/irq.h>
+
 #include "arm.h"
-#include "cp15.h"
 #include "sctlr.h"
 #include "mmu.h"
 #include "chip.h"

arch/arm/src/armv7-a/arm_pghead.S

@@ -25,8 +25,9 @@
 #include <nuttx/config.h>
 #include <nuttx/page.h>
 
+#include <arch/irq.h>
+
 #include "arm.h"
-#include "cp15.h"
 #include "sctlr.h"
 #include "mmu.h"
 #include "chip.h"

arch/arm/src/armv7-a/arm_scu.c

@@ -26,12 +26,13 @@
 
 #include <stdint.h>
 
+#include <arch/irq.h>
+
 #include "arm_internal.h"
 #include "cp15_cacheops.h"
 #include "barriers.h"
 #include "sctlr.h"
 #include "scu.h"
-#include "cp15.h"
 
 /****************************************************************************
  * Public Functions

arch/arm/src/armv7-a/arm_timer.c

@@ -27,10 +27,11 @@
 #include <nuttx/irq.h>
 #include <nuttx/kmalloc.h>
 
+#include <arch/irq.h>
+
 #include "arm_timer.h"
 #include "barriers.h"
 #include "gic.h"
-#include "cp15.h"
 
 /****************************************************************************
  * Pre-processor Definitions

arch/arm/src/armv7-a/arm_vectors.S

@@ -26,7 +26,6 @@
 #include <nuttx/irq.h>
 
 #include "arm.h"
-#include "cp15.h"
 #include "chip.h"
 
 	.file	"arm_vectors.S"

arch/arm/src/armv7-a/sctlr.h

@@ -34,8 +34,9 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/irq.h>
+
 #include "barriers.h"
-#include "cp15.h"
 
 /****************************************************************************
  * Pre-processor Definitions

arch/arm/src/armv7-r/arm_cpuhead.S

@@ -27,7 +27,6 @@
 #include <arch/irq.h>
 
 #include "arm.h"
-#include "cp15.h"
 #include "sctlr.h"
 #include "smp.h"
 #include "chip.h"

arch/arm/src/armv7-r/arm_cpuinfo.c

@@ -26,9 +26,10 @@
 #include <nuttx/config.h>
 #include <nuttx/fs/procfs.h>
 
+#include <arch/irq.h>
+
 #include "arm_internal.h"
 #include "hwcap.h"
-#include "cp15.h"
 
 #if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_CPUINFO)
 

arch/arm/src/armv7-r/arm_fpuconfig.S

@@ -23,7 +23,8 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include "cp15.h"
+
+#include <arch/irq.h>
 
 #ifdef CONFIG_ARCH_FPU
 

arch/arm/src/armv7-r/arm_head.S

@@ -24,8 +24,9 @@
 
 #include <nuttx/config.h>
 
+#include <arch/irq.h>
+
 #include "arm.h"
-#include "cp15.h"
 #include "sctlr.h"
 #include "arm_internal.h"
 

arch/arm/src/armv7-r/arm_scu.c

@@ -26,12 +26,13 @@
 
 #include <stdint.h>
 
+#include <arch/irq.h>
+
 #include "arm_internal.h"
 #include "cp15_cacheops.h"
 #include "barriers.h"
 #include "sctlr.h"
 #include "scu.h"
-#include "cp15.h"
 
 /****************************************************************************
  * Public Functions

arch/arm/src/armv7-r/arm_timer.c

@@ -30,7 +30,6 @@
 #include "arm_timer.h"
 #include "barriers.h"
 #include "gic.h"
-#include "cp15.h"
 
 /****************************************************************************
  * Pre-processor Definitions