PyHDLio

This is the main repository for the pyhdlio Python package, which is intended to support the input and output of HDL source.

Features:

• VHDL object model
• VHDL parsing (source → model)
  • port groups inferred from source proximity (empty lines, comments)
• VHDL output (model → source) (coming soon)
• Verilog object model (planned)
• Verilog parsing (source → model) (planned)
• Verilog output (model → source) (planned)

Usage Example

from pyhdlio.vhdl import Document

document = Document.FromFile("./design.vhd")
for entity in document.Entities.values():
    print(f"Entity: {entity.Identifier}")
    if entity.PortItems:
        for port_item in entity.PortItems:
            print(f"  Port: {port_item.Identifiers[0]}")

Acknowledgements

• Language processing uses ANTLR.
• The VHDL grammar was copied from pyVHDLParser.
• The VHDL object model uses pyVHDLModel.

Installation

It is intended that pyhdlio be installed using pip as shown below. This method is not yet working.

pip install pyhdlio

Alternatively, clone this repository and install the package from it. Note that the -e option makes the package editable.

git clone https://github.com/amb5l/PyHDLio
cd PyHDLio
pip install -e .

Examples

See the examples readme here.

Development

See https://github.com/amb5l/PyHDLio-dev.

License

PyHDLio is distributed under the GNU General Public License v3.0 (GPLv3). See LICENSE.md for details.

For license information on ANTLR, see: ANTLR 4 License.

For license information for pyVHDLModel and pyVHDLParser, see:

• pyVHDLModel on GitHub
• pyVHDLParser on GitHub