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[mlir][dxsa] Add dcl_indexable_temp instruction#120

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[mlir][dxsa] Add dcl_indexable_temp instruction#120
tagolog wants to merge 1 commit intoaccess-softek:dxsa-mlirfrom
tagolog:dxsa-mlir-dcl_indexable_temp

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@tagolog tagolog commented May 1, 2026

Example:
dxsa.dcl_indexable_temp x0[23], 2
dxsa.dcl_indexable_temp x7[4096], 4

@tagolog tagolog requested review from asavonic and asl May 1, 2026 01:49
@tagolog tagolog self-assigned this May 1, 2026
Example:
  dxsa.dcl_indexable_temp x0[23], 2
  dxsa.dcl_indexable_temp x7[4096], 4

Signed-off-by: Vladimir Shiryaev <tagolog@users.noreply.github.com>
@tagolog tagolog force-pushed the dxsa-mlir-dcl_indexable_temp branch from 845ef23 to 0ecbd6a Compare May 1, 2026 03:53
@tagolog tagolog changed the title Add dcl_indexable_temp instruction [mlir][dxsa] Add dcl_indexable_temp instruction May 1, 2026

namespace {

/// Parse a register identifier of the form `<prefix><N>` (e.g. `x0`, `r3`).
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We should consider if custom syntax is worth adding at this point, or at all.
It looks good, but we have a lot of instructions to support.

@tagolog tagolog marked this pull request as draft May 1, 2026 18:18
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2 participants