Refactor CPU feature detection: split x86 and ARM into separate units with shared SIMD level types

[Xor-el]

Summary

Splits the monolithic TCpuFeatures class into architecture-specific units (HlpX86SimdFeatures, HlpArmSimdFeatures) with shared SIMD level enums (HlpSimdLevels), and adds foundational ARM SIMD and target OS defines to the include files.

Motivation

HlpCpuFeatures was a single class that mixed x86-specific CPUID detection logic with the public dispatch API. This made it impossible to extend to ARM without further bloating the unit. The TCpuSimdLevel enum was also x86-specific (SSE2, SSSE3, AVX2) but lived in the shared namespace, leaving no room for ARM SIMD levels.

All dispatch units (HlpBlake2BDispatch, HlpSHA2_256Dispatch, etc.) called TCpuFeatures.GetActiveLevel() and matched against TCpuSimdLevel.* — semantically x86 concepts that were presented as architecture-neutral.

Changes

New units

• HlpSimdLevels — defines TX86SimdLevel (Scalar, SSE2, SSSE3, AVX2) and TArmSimdLevel (Scalar, NEON, SVE, SVE2) as separate enums.
• HlpX86SimdFeatures — TX86SimdFeatures class containing all CPUID/XGETBV inline assembly, hardware probing, build-time override logic, and cached feature flags. Moved from HlpCpuFeatures with the addition of HasAESNI() detection (CPUID leaf 1, ECX bit 25).
• HlpArmSimdFeatures — TArmSimdFeatures class with stub detection methods for NEON, SVE, SVE2, and crypto extensions (AES, SHA1, SHA256, SHA512, SHA3, PMULL). All detection methods currently return False (marked TODO), providing the scaffolding for future ARM SIMD dispatch.

Refactored HlpCpuFeatures

TCpuFeatures is now a thin facade with two class properties:

• TCpuFeatures.X86 → returns TX86SimdFeatures
• TCpuFeatures.Arm → returns TArmSimdFeatures

All CPUID logic, class vars, and the initialization section have been removed from this unit. Detection now runs in each architecture-specific unit's own initialization block.

Dispatch unit updates

All 12 dispatch units updated to use the new API:

• TCpuFeatures.GetActiveLevel() → TCpuFeatures.X86.GetSimdLevel()
• TCpuSimdLevel.* → TX86SimdLevel.*
• TCpuFeatures.HasSHANI() → TCpuFeatures.X86.HasSHANI()
• TCpuFeatures.HasPCLMULQDQ() → TCpuFeatures.X86.HasPCLMULQDQ()
• TCpuFeatures.HasVPCLMULQDQ() → TCpuFeatures.X86.HasVPCLMULQDQ()
• Added HlpSimdLevels to each dispatch unit's uses clause.

Affected dispatch units: Adler32, CRC, Blake2B, Blake2S, Blake3, SHA1, SHA2-256, SHA2-512, SHA3, XXHash3, Argon2, Scrypt.

Include file additions

HashLib.inc (Delphi):

• Added HASHLIB_ARM and HASHLIB_AARCH64 CPU architecture defines.
• Added target OS defines: HASHLIB_MSWINDOWS, HASHLIB_IOS, HASHLIB_MACOS, HASHLIB_ANDROID, HASHLIB_LINUX.
• Added HASHLIB_ARM_SIMD composite define (mirrors existing HASHLIB_X86_SIMD).
• Added ARM force-dispatch options (HASHLIB_FORCE_NEON, HASHLIB_FORCE_SVE) with mutual exclusion compile-time check.

HashLibFPC.inc (FPC):

• Added HASHLIB_ARM / HASHLIB_ARM_ASM and HASHLIB_AARCH64 / HASHLIB_AARCH64_ASM defines.
• Added target OS defines: HASHLIB_MSWINDOWS, HASHLIB_ANDROID, HASHLIB_IOS, HASHLIB_MACOS, HASHLIB_BSD, HASHLIB_LINUX, HASHLIB_SOLARIS.