feat: M5 Tab5 + Metro RP2350 HSTX configs; TFT_eSPI parity doc#54
Merged
Conversation
Add MP/CP board configs for M5 Tab5 (ILI9881C DSI + GT911) and Adafruit Metro RP2350 HSTX DVI breakout. Add Teensy 4.1 FlexIO ILI9341 i80bus config, Tab5 init/IO-expander drivers, RP2350 gpio_pin SIO base, and port-by-port TFT_eSPI parity documentation. Fix cp_mimxrt1170 DSI config to use CircuitPython mipidsi. Co-authored-by: bbarnett <bbarnett@gmail.com>
Contributor
|
Bugbot is not enabled for your account, so this pull request was not reviewed. Enable Bugbot in the Cursor dashboard to get automatic reviews on future PRs. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
i80busboard config for MIMXRT1062 FlexIO2 8080docs/hardware/tft-espi-parity.md): port-by-port mapping of SPI/I80/RGB/DSI/DVI coveragecp_mimxrt1170_evk_waveshare_5dsito use CPmipidsi(not displayif import)gpio_pin.py: RP2350 SIO base addressCaveats
t-rgb_480remains MP-only (no CP sibling)Test plan