[TRTLLM-14388][refactor] BREAKING: Remove 2-model code and tests - #16380
[TRTLLM-14388][refactor] BREAKING: Remove 2-model code and tests#16380mikeiovine wants to merge 4 commits into
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tensorrt_llm/_torch/attention_backend/sparse/dsa.py (1)
1531-1541: 🚀 Performance & Scalability | 🔵 Trivial | ⚡ Quick winPer-step pinned host buffer allocation in a hot path.
host_block_tableis freshly allocated (withpin_memory=prefer_pinned()) on every call toprepare_for_indexer_k_cache, which runs every forward step viaprepare(). Every sibling staging buffer in this class (host_indexer_k_cache_block_offsets,host_slot_mapping_fp8, etc.) is pre-allocated once increate_buffers_for_indexer/__post_init__and reused. Repeated pinned-memory allocation/free is a comparatively costly page-locking operation on a per-forward-step path.♻️ Suggested fix: pre-allocate a persistent staging buffer
- # pool_indices already has correct values; set padding to -1. - # Stage through a fresh pinned buffer: an async H2D from pageable - # memory would block the host behind the busy execution stream. - host_block_table = torch.empty((pool_indices.shape[0], max_blocks_used), - dtype=pool_indices.dtype, - pin_memory=prefer_pinned()) - host_block_table.copy_(pool_indices[:, :max_blocks_used]) + # pool_indices already has correct values; set padding to -1. + # Stage through a persistent pinned buffer (allocated once in + # create_buffers_for_indexer) to avoid a per-step pinned alloc. + host_block_table = self.host_block_table_staging[:pool_indices.shape[0], :max_blocks_used] + host_block_table.copy_(pool_indices[:, :max_blocks_used])And add a
self.host_block_table_stagingbuffer of shape[max_num_sequences, max_blocks_per_seq]alongside the other persistent host buffers increate_buffers_for_indexer.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/attention_backend/sparse/dsa.py` around lines 1531 - 1541, Pre-allocate a persistent host_block_table_staging buffer in create_buffers_for_indexer (or the corresponding __post_init__ setup) with shape [max_num_sequences, max_blocks_per_seq], matching pool_indices’ dtype and pinned-memory policy. Update prepare_for_indexer_k_cache to reuse this buffer for copying and padding instead of allocating host_block_table on every call, while preserving the existing per-step contents and masking behavior.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Nitpick comments:
In `@tensorrt_llm/_torch/attention_backend/sparse/dsa.py`:
- Around line 1531-1541: Pre-allocate a persistent host_block_table_staging
buffer in create_buffers_for_indexer (or the corresponding __post_init__ setup)
with shape [max_num_sequences, max_blocks_per_seq], matching pool_indices’ dtype
and pinned-memory policy. Update prepare_for_indexer_k_cache to reuse this
buffer for copying and padding instead of allocating host_block_table on every
call, while preserving the existing per-step contents and masking behavior.
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- tests/unittest/_torch/executor/test_dual_pool_kv_cache.py
- examples/auto_deploy/model_registry/configs/super_v3_mtp.yaml
- tests/scripts/perf-sanity/disaggregated/gb300_kimi-k25-thinking-fp4_8k1k_con4_ctx1_dep4_gen1_tep8_eplb0_mtp3_ccb-NIXL.yaml
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- docs/source/blogs/tech_blog/blog06_Llama4_maverick_eagle_guide.md
- docs/source/features/torch_compile_and_piecewise_cuda_graph.md
- tensorrt_llm/_torch/auto_deploy/shim/ad_executor.py
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Signed-off-by: Mike Iovine <miovine@nvidia.com>
Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
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Actionable comments posted: 1
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@docs/source/legacy/advanced/speculative-decoding.md`:
- Line 178: Add the repository-standard NVIDIA copyright header to the top of
the modified speculative-decoding documentation file, with the copyright year
updated through 2026. Preserve the existing content unchanged.
🪄 Autofix (Beta)
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
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.pre-commit-config.yamldocs/source/blogs/tech_blog/blog06_Llama4_maverick_eagle_guide.mddocs/source/features/torch_compile_and_piecewise_cuda_graph.mddocs/source/legacy/advanced/speculative-decoding.mdexamples/auto_deploy/model_registry/configs/super_v3_mtp.yamlexamples/llm-api/llm_speculative_decoding.pyexamples/llm-api/quickstart_advanced.pyexamples/models/core/deepseek_v4/README.mdexamples/models/core/exaone/README.mdexamples/models/core/mistral_large_3/README.mdexamples/models/core/nemotron/README_nemotron_super_v3.mdlegacy-files.txtpyproject.tomlruff-legacy.tomltensorrt_llm/_torch/attention_backend/interface.pytensorrt_llm/_torch/attention_backend/sparse/dsa.pytensorrt_llm/_torch/attention_backend/trtllm.pytensorrt_llm/_torch/auto_deploy/llm_args.pytensorrt_llm/_torch/auto_deploy/shim/ad_executor.pytensorrt_llm/_torch/models/modeling_auto.pytensorrt_llm/_torch/models/modeling_deepseekv3.pytensorrt_llm/_torch/models/modeling_glm.pytensorrt_llm/_torch/models/modeling_nemotron_h.py
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- pyproject.toml
- legacy-files.txt
- examples/models/core/nemotron/README_nemotron_super_v3.md
- ruff-legacy.toml
- tensorrt_llm/_torch/models/modeling_auto.py
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- tensorrt_llm/_torch/attention_backend/sparse/dsa.py
- tensorrt_llm/_torch/models/modeling_nemotron_h.py
- examples/llm-api/quickstart_advanced.py
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- tensorrt_llm/_torch/auto_deploy/shim/ad_executor.py
- docs/source/blogs/tech_blog/blog06_Llama4_maverick_eagle_guide.md
- examples/llm-api/llm_speculative_decoding.py
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The 2-model removal deleted Eagle3SpecMetadata and every producer of request_accepted_path but left one use behind, which would raise NameError on any speculative decoding step. Also tighten the legacy ruff baseline to match the current tree. Signed-off-by: Mike Iovine <miovine@nvidia.com>
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Description
Remove 2-model code and related tests. We are past the deprecation period and all feature gaps have been closed.
Some 2-model code is left behind for a few niche things that can't use 1-model (ngram, user-provided).
Test Coverage
Existing tests.
PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
If PR introduces API changes, an appropriate PR label is added - either
api-compatibleorapi-breaking. Forapi-breaking, includeBREAKINGin the PR title.Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
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/bot help.Dev Engineer Review
ModelDrafter,MTPDraftModelForCausalLM,Eagle3SpecMetadata, and related CUDA-graph and KV-cache branches.eagle3_one_model,mtp_eagle_one_model,is_draft_model, anddraft_model_engine.QA Engineer Review
test_draft_token_prepare_for_generationandtest_draft_token_tree_sampling.test_eagle3,test_eagle3_spec_decoding_stats,test_multi_eagle3,test_get_num_spec_layers_*,test_accepts_mtp_eagle,test_detect_hidden_states_capture_last_layer_for_mtp_eagle, andtest_autodeploy_eagle3_acceptance_rate.tests/integration/test_lists/test-db/,tests/integration/test_lists/qa/, andtests/integration/test_lists/waives.txtwhere applicable.l0_b200.yml.