Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
MAC		MAC
MAC_components		MAC_components
FYP Project Plan - January.xlsx		FYP Project Plan - January.xlsx
FYP Project Plan - March.xlsx		FYP Project Plan - March.xlsx
FYP Project Plan - October.xlsx		FYP Project Plan - October.xlsx
LICENSE		LICENSE
Open Source Ethernet MAC.pdf		Open Source Ethernet MAC.pdf
README.md		README.md
Table.xlsx		Table.xlsx
Verilog Open Source Ethernet MAC.pptx		Verilog Open Source Ethernet MAC.pptx
arbiter.v		arbiter.v
arbiter_tb.v		arbiter_tb.v
backoff.xlsx		backoff.xlsx
clock_divider.v		clock_divider.v
crc.v		crc.v
crc.xlsx		crc.xlsx
gmii.v		gmii.v
mii.v		mii.v
mii.xlsx		mii.xlsx
out		out
priority_encoder.v		priority_encoder.v
random.v		random.v
rgmii.v		rgmii.v
rgmii.xlsx		rgmii.xlsx
rmii.v		rmii.v
rmii.xlsx		rmii.xlsx
rx.dot		rx.dot
rx.v		rx.v
rx.xlsx		rx.xlsx
schematic.pdf		schematic.pdf
sme.xlsx		sme.xlsx
station_management.v		station_management.v
station_management_mdo_mdi.v		station_management_mdo_mdi.v
station_management_mdo_mdi_tb.v		station_management_mdo_mdi_tb.v
station_management_tb.v		station_management_tb.v
test.vcd		test.vcd
tx.v		tx.v
tx.xlsx		tx.xlsx