Add alpha support for 9.7 data processing intrinsics by rockdreamer · Pull Request #428 · ARM-software/acle

rockdreamer · 2026-01-30T13:24:06Z

name: Add alpha support for 9.7 data processing intrinsics
about: feature proposal.

This change adds intrinsics for the following architectural features:

FEAT_F16F32DOT
FEAT_F16F32MM
FEAT_F16MM
FEAT_SVE_B16MM
FEAT_SVE2p3
FEAT_SME2p3

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main/acle.md

This change adds - AdvSIMD dot intrinsics available under FEAT_F16F32DOT - SVE dot intrinsics available under either FEAT_SVE2p3 || FEAT_SME2p3

This change adds - AdvSIMD intrinsics based on FMMLA available under FEAT_F16F32MM and FEAT_F16MM - SVE intrinsics available under either FEAT_F16MM and FEAT_SVE_B16MM

This change adds support for the svluti6 operations under FEAT_SVE2p3 and FEAT_SME2p3.

This change adds support for the svaddqp, svaddsubp and svsubp operations under FEAT_SVE2p3 and FEAT_SME2p3.

This change adds support for the svcvt* operations under FEAT_SVE2p3 and FEAT_SME2p3.

This change adds support for the svaba operations under FEAT_SVE2p3 and FEAT_SME2p3.

This change adds support for new svqshrn, svqshrun operations under FEAT_SVE2p3 and FEAT_SME2p3.

ricbal02 · 2026-02-27T16:48:59Z

neon_intrinsics/advsimd.md

+|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------|--------------------------------|-------------------|---------------------------|
+| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vfdot_f32_f16" target="_blank">vfdot_f32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t r,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x4_t b)</code>                                                         | `r -> Vd.2S`<br>`a -> Vn.4H`<br>`b -> Vm.4H`                     | `FDOT Vd.2S,Vn.4H,Vm.4H`       | `Vd.2S -> result` | `A64`                     |
+| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vfdotq_f32_f16" target="_blank">vfdotq_f32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t r,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x8_t b)</code>                                                       | `r -> Vd.4S`<br>`a -> Vn.8H`<br>`b -> Vm.8H`                     | `FDOT Vd.4S,Vn.8H,Vm.8H`       | `Vd.4S -> result` | `A64`                     |
+| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vfdot_lane_f32_f16" target="_blank">vfdot_lane_f32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t r,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x2_t b,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>   | `r -> Vd.2S`<br>`a -> Vn.4H`<br>`b -> Vm.2H`<br>`0 <= lane <= 3` | `FDOT Vd.2S,Vn.4H,Vm.2H[lane]` | `Vd.2S -> result` | `A64`                     |


float16x4_t b for vfdot_lane and
float16x8_t b for vfdot_laneq

georges-arm · 2026-03-03T15:16:42Z

main/acle.md

 ``` c
-  // Variants are also available for _s32_s16 and _u32_u16
+  // Variants are also available for _s32_s16, _u32_u16
+  // and also for _s16_s8 and _u16_u8 if (__ARM_FEATURE_SVE2p3 __ARM || _FEATURE_SME2p3).


__ARM seems misplaced here?

georges-arm · 2026-03-03T15:16:55Z

main/acle.md

 ``` c
-  // Variants are also available for _s32_s16 and _u32_u16
+  // Variants are also available for _s32_s16, _u32_u16
+  // and also for _s16_s8 and _u16_u8  if (__ARM_FEATURE_SVE2p3 __ARM || _FEATURE_SME2p3).


__ARM seems misplaced here?

georges-arm · 2026-03-03T15:18:04Z

main/acle.md

+[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
+extended in the future.
+
+`__ARM_FEATURE_F16F32MM` is defined if the NEON half-precision matrix multiply


NEON should be Neon. Same everywhere else.

georges-arm · 2026-03-03T15:18:24Z

main/acle.md


 ### SVE2 floating-point matrix multiply-accumulate instructions.

+#### BFMMLA, FMMLA(non-widening)


Space before ( ?

georges-arm · 2026-03-03T15:20:25Z

main/acle.md

+
+#### FCVTZSN, FCVTZUN
+
+Floating-point narrowing convert to interleaved integer, rounding toward zero


Missing full-stop (.) at end of this line, possibly others?

georges-arm · 2026-03-03T15:22:14Z

main/acle.md

+  // Variants are also available for
+  //            _s32[_s16], _s64[_s32],
+  // _u16[_u8], _u32[_u16], _u64[_u32].
+  svint16_t svaba_s16[_s8](svint16_t zda, svint8_t zn, svint8_t zm);


In other widening intrinsics we include l in the intrinsic name, so this should be svabal ?

georges-arm · 2026-03-03T15:24:55Z

main/acle.md

+  // Variants are also available for
+  //               _s16[_f32_x2], _s32[_f64_x2],
+  // _u8[_f16_x2], _u16[_f32_x2], _u32[_f64_x2].
+  svint8_t svcvt_s8[_f16_x2](svfloat16x2_t zn);


Other narrowing conversions have different naming - they include the suffix, e.g. svcvtxnt, so should this be svsvcntzn or similar?

amilendra · 2026-03-04T10:56:06Z

main/acle.md

+  // Variants are also available for
+  //            _s32[_s16], _s64[_s32],
+  // _u16[_u8], _u32[_u16], _u64[_u32].
+  svint16_t svaba_s16[_s8](svint16_t zda, svint8_t zn, svint8_t zm);


Can't we do svint16_t svaba[_s16_s8](svint16_t zda, svint8_t zn, svint8_t zm);?
Or is svint16_t svaba(svint16_t zda, svint8_t zn, svint8_t zm); already defined elsewhere?

georges-arm reviewed Feb 2, 2026

View reviewed changes

rockdreamer added 8 commits February 5, 2026 11:01

Update copyright dates

2739bfa

Add alpha support for 9.7 dot product intrinsics

a057be6

This change adds - AdvSIMD dot intrinsics available under FEAT_F16F32DOT - SVE dot intrinsics available under either FEAT_SVE2p3 || FEAT_SME2p3

Add alpha support for 9.7 mmla intrinsics

d3f2e4e

This change adds - AdvSIMD intrinsics based on FMMLA available under FEAT_F16F32MM and FEAT_F16MM - SVE intrinsics available under either FEAT_F16MM and FEAT_SVE_B16MM

Add alpha support for 9.7 lookup table intrinsics

3a64c96

This change adds support for the svluti6 operations under FEAT_SVE2p3 and FEAT_SME2p3.

Add alpha support for 9.7 pairwise operation intrinsics

8e44205

This change adds support for the svaddqp, svaddsubp and svsubp operations under FEAT_SVE2p3 and FEAT_SME2p3.

Add alpha support for 9.7 conversion intrinsics

752c7cc

This change adds support for the svcvt* operations under FEAT_SVE2p3 and FEAT_SME2p3.

Add alpha support for 9.7 absolute difference accumulation intrinsics

6365c01

This change adds support for the svaba operations under FEAT_SVE2p3 and FEAT_SME2p3.

Add alpha support for 9.7 shift right narrow intrinsics

f0458c9

This change adds support for new svqshrn, svqshrun operations under FEAT_SVE2p3 and FEAT_SME2p3.

rockdreamer force-pushed the dp97 branch from 5b93d9b to f0458c9 Compare February 5, 2026 11:45

ricbal02 reviewed Feb 27, 2026

View reviewed changes

georges-arm reviewed Mar 3, 2026

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amilendra reviewed Mar 4, 2026

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Add alpha support for 9.7 data processing intrinsics#428

Add alpha support for 9.7 data processing intrinsics#428
rockdreamer wants to merge 8 commits intoARM-software:mainfrom
rockdreamer:dp97

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		### SVE2 floating-point matrix multiply-accumulate instructions.

		#### BFMMLA, FMMLA(non-widening)


		#### FCVTZSN, FCVTZUN

		Floating-point narrowing convert to interleaved integer, rounding toward zero

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rockdreamer commented Jan 30, 2026

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ricbal02 Feb 27, 2026 •

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