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Zhang Pengdbaluta
Zhang Peng
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dbaluta
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drivers: cavs: dmic: Remove dmic_read/write/update_bits functions
Remove dmic_read/write/update_bits functions, instead by dai_read/ write/update_bits functions. Signed-off-by: Zhang Peng <peng_zhang_8@nxp.com>
1 parent 6fa4e4c commit 0d54df1

1 file changed

Lines changed: 86 additions & 102 deletions

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‎src/drivers/intel/cavs/dmic.c‎

Lines changed: 86 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -151,22 +151,6 @@ static const uint32_t coef_base_b[4] = {PDM0_COEFFICIENT_B, PDM1_COEFFICIENT_B,
151151
static struct sof_ipc_dai_dmic_params *dmic_prm[DMIC_HW_FIFOS];
152152
static int dmic_active_fifos;
153153

154-
static void dmic_write(struct dai *dai, uint32_t reg, uint32_t value)
155-
{
156-
dai_write(dai, reg, value);
157-
}
158-
159-
static uint32_t dmic_read(struct dai *dai, uint32_t reg)
160-
{
161-
return dai_read(dai, reg);
162-
}
163-
164-
static void dmic_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
165-
uint32_t value)
166-
{
167-
dai_update_bits(dai, reg, mask, value);
168-
}
169-
170154
/* this ramps volume changes over time */
171155
static enum task_state dmic_work(void *data)
172156
{
@@ -204,31 +188,31 @@ static enum task_state dmic_work(void *data)
204188
continue;
205189

206190
if (dmic->startcount == DMIC_UNMUTE_CIC)
207-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
208-
CIC_CONTROL_MIC_MUTE_BIT, 0);
191+
dai_update_bits(dai, base[i] + CIC_CONTROL,
192+
CIC_CONTROL_MIC_MUTE_BIT, 0);
209193

210194
if (dmic->startcount == DMIC_UNMUTE_FIR) {
211195
switch (dai->index) {
212196
case 0:
213-
dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
214-
FIR_CONTROL_A_MUTE_BIT, 0);
197+
dai_update_bits(dai, base[i] + FIR_CONTROL_A,
198+
FIR_CONTROL_A_MUTE_BIT, 0);
215199
break;
216200
case 1:
217-
dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
218-
FIR_CONTROL_B_MUTE_BIT, 0);
201+
dai_update_bits(dai, base[i] + FIR_CONTROL_B,
202+
FIR_CONTROL_B_MUTE_BIT, 0);
219203
break;
220204
}
221205
}
222206
switch (dai->index) {
223207
case 0:
224208
val = OUT_GAIN_LEFT_A_GAIN(gval);
225-
dmic_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
226-
dmic_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
209+
dai_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
210+
dai_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
227211
break;
228212
case 1:
229213
val = OUT_GAIN_LEFT_B_GAIN(gval);
230-
dmic_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
231-
dmic_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
214+
dai_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
215+
dai_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
232216
break;
233217
}
234218
}
@@ -859,7 +843,7 @@ static int configure_registers(struct dai *dai,
859843
OUTCONTROL0_OF(of0) |
860844
OUTCONTROL0_IPM(ipm) |
861845
OUTCONTROL0_TH(th);
862-
dmic_write(dai, OUTCONTROL0, val);
846+
dai_write(dai, OUTCONTROL0, val);
863847
trace_dmic("configure_registers(), OUTCONTROL0 = %u", val);
864848

865849
ipm_helper1(&ipm, 1);
@@ -871,7 +855,7 @@ static int configure_registers(struct dai *dai,
871855
OUTCONTROL1_OF(of1) |
872856
OUTCONTROL1_IPM(ipm) |
873857
OUTCONTROL1_TH(th);
874-
dmic_write(dai, OUTCONTROL1, val);
858+
dai_write(dai, OUTCONTROL1, val);
875859
trace_dmic("configure_registers(), OUTCONTROL1 = %u", val);
876860
#endif
877861

@@ -889,7 +873,7 @@ static int configure_registers(struct dai *dai,
889873
OUTCONTROL0_IPM_SOURCE_3(source[2]) |
890874
OUTCONTROL0_IPM_SOURCE_4(source[3]) |
891875
OUTCONTROL0_TH(th);
892-
dmic_write(dai, OUTCONTROL0, val);
876+
dai_write(dai, OUTCONTROL0, val);
893877
trace_dmic("configure_registers(), OUTCONTROL0 = %u", val);
894878

895879
ipm_helper2(source, &ipm, 1);
@@ -905,7 +889,7 @@ static int configure_registers(struct dai *dai,
905889
OUTCONTROL1_IPM_SOURCE_3(source[2]) |
906890
OUTCONTROL1_IPM_SOURCE_4(source[3]) |
907891
OUTCONTROL1_TH(th);
908-
dmic_write(dai, OUTCONTROL1, val);
892+
dai_write(dai, OUTCONTROL1, val);
909893
trace_dmic("configure_registers(), OUTCONTROL1 = %u", val);
910894
#endif
911895

@@ -932,12 +916,12 @@ static int configure_registers(struct dai *dai,
932916
CIC_CONTROL_MIC_A_POLARITY(dmic_prm[di]->pdm[i].polarity_mic_b) |
933917
CIC_CONTROL_MIC_MUTE(cic_mute) |
934918
CIC_CONTROL_STEREO_MODE(stereo[i]);
935-
dmic_write(dai, base[i] + CIC_CONTROL, val);
919+
dai_write(dai, base[i] + CIC_CONTROL, val);
936920
trace_dmic("configure_registers(), CIC_CONTROL = %u", val);
937921

938922
val = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) |
939923
CIC_CONFIG_COMB_COUNT(cfg->mcic - 1);
940-
dmic_write(dai, base[i] + CIC_CONFIG, val);
924+
dai_write(dai, base[i] + CIC_CONFIG, val);
941925
trace_dmic("configure_registers(), CIC_CONFIG = %u", val);
942926

943927
/* Mono right channel mic usage requires swap of PDM channels
@@ -953,7 +937,7 @@ static int configure_registers(struct dai *dai,
953937
MIC_CONTROL_CLK_EDGE(edge) |
954938
MIC_CONTROL_PDM_EN_B(cic_start_b) |
955939
MIC_CONTROL_PDM_EN_A(cic_start_a);
956-
dmic_write(dai, base[i] + MIC_CONTROL, val);
940+
dai_write(dai, base[i] + MIC_CONTROL, val);
957941
trace_dmic("configure_registers(), MIC_CONTROL = %u", val);
958942

959943
/* FIR A */
@@ -964,31 +948,31 @@ static int configure_registers(struct dai *dai,
964948
FIR_CONTROL_A_DCCOMP(dccomp) |
965949
FIR_CONTROL_A_MUTE(fir_mute) |
966950
FIR_CONTROL_A_STEREO(stereo[i]);
967-
dmic_write(dai, base[i] + FIR_CONTROL_A, val);
951+
dai_write(dai, base[i] + FIR_CONTROL_A, val);
968952
trace_dmic("configure_registers(), FIR_CONTROL_A = %u", val);
969953

970954
val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) |
971955
FIR_CONFIG_A_FIR_SHIFT(cfg->fir_a_shift) |
972956
FIR_CONFIG_A_FIR_LENGTH(fir_length);
973-
dmic_write(dai, base[i] + FIR_CONFIG_A, val);
957+
dai_write(dai, base[i] + FIR_CONFIG_A, val);
974958
trace_dmic("configure_registers(), FIR_CONFIG_A = %u", val);
975959

976960
val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0);
977-
dmic_write(dai, base[i] + DC_OFFSET_LEFT_A, val);
961+
dai_write(dai, base[i] + DC_OFFSET_LEFT_A, val);
978962
trace_dmic("configure_registers(), DC_OFFSET_LEFT_A = %u",
979963
val);
980964

981965
val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0);
982-
dmic_write(dai, base[i] + DC_OFFSET_RIGHT_A, val);
966+
dai_write(dai, base[i] + DC_OFFSET_RIGHT_A, val);
983967
trace_dmic("configure_registers(), DC_OFFSET_RIGHT_A = %u",
984968
val);
985969

986970
val = OUT_GAIN_LEFT_A_GAIN(0);
987-
dmic_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
971+
dai_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
988972
trace_dmic("configure_registers(), OUT_GAIN_LEFT_A = %u", val);
989973

990974
val = OUT_GAIN_RIGHT_A_GAIN(0);
991-
dmic_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
975+
dai_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
992976
trace_dmic("configure_registers(), OUT_GAIN_RIGHT_A = %u", val);
993977

994978
/* FIR B */
@@ -999,30 +983,30 @@ static int configure_registers(struct dai *dai,
999983
FIR_CONTROL_B_DCCOMP(dccomp) |
1000984
FIR_CONTROL_B_MUTE(fir_mute) |
1001985
FIR_CONTROL_B_STEREO(stereo[i]);
1002-
dmic_write(dai, base[i] + FIR_CONTROL_B, val);
986+
dai_write(dai, base[i] + FIR_CONTROL_B, val);
1003987
trace_dmic("configure_registers(), FIR_CONTROL_B = %u", val);
1004988

1005989
val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) |
1006990
FIR_CONFIG_B_FIR_SHIFT(cfg->fir_b_shift) |
1007991
FIR_CONFIG_B_FIR_LENGTH(fir_length);
1008-
dmic_write(dai, base[i] + FIR_CONFIG_B, val);
992+
dai_write(dai, base[i] + FIR_CONFIG_B, val);
1009993
trace_dmic("configure_registers(), FIR_CONFIG_B = %u", val);
1010994

1011995
val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0);
1012-
dmic_write(dai, base[i] + DC_OFFSET_LEFT_B, val);
996+
dai_write(dai, base[i] + DC_OFFSET_LEFT_B, val);
1013997
trace_dmic("configure_registers(), DC_OFFSET_LEFT_B = %u", val);
1014998

1015999
val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0);
1016-
dmic_write(dai, base[i] + DC_OFFSET_RIGHT_B, val);
1000+
dai_write(dai, base[i] + DC_OFFSET_RIGHT_B, val);
10171001
trace_dmic("configure_registers(), DC_OFFSET_RIGHT_B = %u",
10181002
val);
10191003

10201004
val = OUT_GAIN_LEFT_B_GAIN(0);
1021-
dmic_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
1005+
dai_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
10221006
trace_dmic("configure_registers(), OUT_GAIN_LEFT_B = %u", val);
10231007

10241008
val = OUT_GAIN_RIGHT_B_GAIN(0);
1025-
dmic_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
1009+
dai_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
10261010
trace_dmic("configure_registers(), OUT_GAIN_RIGHT_B = %u", val);
10271011

10281012
/* Write coef RAM A with scaled coefficient in reverse order */
@@ -1032,7 +1016,7 @@ static int configure_registers(struct dai *dai,
10321016
(int64_t)cfg->fir_a->coef[j], cfg->fir_a_scale,
10331017
31, DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
10341018
cu = FIR_COEF_A(ci);
1035-
dmic_write(dai, coef_base_a[i]
1019+
dai_write(dai, coef_base_a[i]
10361020
+ ((length - j - 1) << 2), cu);
10371021
}
10381022

@@ -1043,7 +1027,7 @@ static int configure_registers(struct dai *dai,
10431027
(int64_t)cfg->fir_b->coef[j], cfg->fir_b_scale,
10441028
31, DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
10451029
cu = FIR_COEF_B(ci);
1046-
dmic_write(dai, coef_base_b[i]
1030+
dai_write(dai, coef_base_b[i]
10471031
+ ((length - j - 1) << 2), cu);
10481032
}
10491033
}
@@ -1253,18 +1237,18 @@ static void dmic_start(struct dai *dai)
12531237
/* Clear FIFO A initialize, Enable interrupts to DSP,
12541238
* Start FIFO A packer.
12551239
*/
1256-
dmic_update_bits(dai, OUTCONTROL0,
1257-
OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
1258-
OUTCONTROL0_SIP_BIT);
1240+
dai_update_bits(dai, OUTCONTROL0,
1241+
OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
1242+
OUTCONTROL0_SIP_BIT);
12591243
break;
12601244
case 1:
12611245
trace_dmic("dmic_start(), dmic->fifo_b");
12621246
/* Clear FIFO B initialize, Enable interrupts to DSP,
12631247
* Start FIFO B packer.
12641248
*/
1265-
dmic_update_bits(dai, OUTCONTROL1,
1266-
OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
1267-
OUTCONTROL1_SIP_BIT);
1249+
dai_update_bits(dai, OUTCONTROL1,
1250+
OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
1251+
OUTCONTROL1_SIP_BIT);
12681252
}
12691253

12701254
for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
@@ -1293,42 +1277,42 @@ static void dmic_start(struct dai *dai)
12931277
* This makes sure we do not clear start/en for another DAI.
12941278
*/
12951279
if (mic_a && mic_b) {
1296-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
1297-
CIC_CONTROL_CIC_START_A_BIT |
1298-
CIC_CONTROL_CIC_START_B_BIT,
1299-
CIC_CONTROL_CIC_START_A(1) |
1300-
CIC_CONTROL_CIC_START_B(1));
1301-
dmic_update_bits(dai, base[i] + MIC_CONTROL,
1302-
MIC_CONTROL_PDM_EN_A_BIT |
1303-
MIC_CONTROL_PDM_EN_B_BIT,
1304-
MIC_CONTROL_PDM_EN_A(1) |
1305-
MIC_CONTROL_PDM_EN_B(1));
1280+
dai_update_bits(dai, base[i] + CIC_CONTROL,
1281+
CIC_CONTROL_CIC_START_A_BIT |
1282+
CIC_CONTROL_CIC_START_B_BIT,
1283+
CIC_CONTROL_CIC_START_A(1) |
1284+
CIC_CONTROL_CIC_START_B(1));
1285+
dai_update_bits(dai, base[i] + MIC_CONTROL,
1286+
MIC_CONTROL_PDM_EN_A_BIT |
1287+
MIC_CONTROL_PDM_EN_B_BIT,
1288+
MIC_CONTROL_PDM_EN_A(1) |
1289+
MIC_CONTROL_PDM_EN_B(1));
13061290
} else if (mic_a) {
1307-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
1308-
CIC_CONTROL_CIC_START_A_BIT,
1309-
CIC_CONTROL_CIC_START_A(1));
1310-
dmic_update_bits(dai, base[i] + MIC_CONTROL,
1311-
MIC_CONTROL_PDM_EN_A_BIT,
1312-
MIC_CONTROL_PDM_EN_A(1));
1291+
dai_update_bits(dai, base[i] + CIC_CONTROL,
1292+
CIC_CONTROL_CIC_START_A_BIT,
1293+
CIC_CONTROL_CIC_START_A(1));
1294+
dai_update_bits(dai, base[i] + MIC_CONTROL,
1295+
MIC_CONTROL_PDM_EN_A_BIT,
1296+
MIC_CONTROL_PDM_EN_A(1));
13131297
} else if (mic_b) {
1314-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
1315-
CIC_CONTROL_CIC_START_B_BIT,
1316-
CIC_CONTROL_CIC_START_B(1));
1317-
dmic_update_bits(dai, base[i] + MIC_CONTROL,
1318-
MIC_CONTROL_PDM_EN_B_BIT,
1319-
MIC_CONTROL_PDM_EN_B(1));
1298+
dai_update_bits(dai, base[i] + CIC_CONTROL,
1299+
CIC_CONTROL_CIC_START_B_BIT,
1300+
CIC_CONTROL_CIC_START_B(1));
1301+
dai_update_bits(dai, base[i] + MIC_CONTROL,
1302+
MIC_CONTROL_PDM_EN_B_BIT,
1303+
MIC_CONTROL_PDM_EN_B(1));
13201304
}
13211305

13221306
switch (dai->index) {
13231307
case 0:
1324-
dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
1325-
FIR_CONTROL_A_START_BIT,
1326-
FIR_CONTROL_A_START(fir_a));
1308+
dai_update_bits(dai, base[i] + FIR_CONTROL_A,
1309+
FIR_CONTROL_A_START_BIT,
1310+
FIR_CONTROL_A_START(fir_a));
13271311
break;
13281312
case 1:
1329-
dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
1330-
FIR_CONTROL_B_START_BIT,
1331-
FIR_CONTROL_B_START(fir_b));
1313+
dai_update_bits(dai, base[i] + FIR_CONTROL_B,
1314+
FIR_CONTROL_B_START_BIT,
1315+
FIR_CONTROL_B_START(fir_b));
13321316
break;
13331317
}
13341318
}
@@ -1337,8 +1321,8 @@ static void dmic_start(struct dai *dai)
13371321
* start capture in sync.
13381322
*/
13391323
for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
1340-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
1341-
CIC_CONTROL_SOFT_RESET_BIT, 0);
1324+
dai_update_bits(dai, base[i] + CIC_CONTROL,
1325+
CIC_CONTROL_SOFT_RESET_BIT, 0);
13421326
}
13431327

13441328
dmic_active_fifos++;
@@ -1377,14 +1361,14 @@ static void dmic_stop(struct dai *dai)
13771361
/* Stop FIFO packers and set FIFO initialize bits */
13781362
switch (dai->index) {
13791363
case 0:
1380-
dmic_update_bits(dai, OUTCONTROL0,
1381-
OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
1382-
OUTCONTROL0_FINIT_BIT);
1364+
dai_update_bits(dai, OUTCONTROL0,
1365+
OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
1366+
OUTCONTROL0_FINIT_BIT);
13831367
break;
13841368
case 1:
1385-
dmic_update_bits(dai, OUTCONTROL1,
1386-
OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
1387-
OUTCONTROL1_FINIT_BIT);
1369+
dai_update_bits(dai, OUTCONTROL1,
1370+
OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
1371+
OUTCONTROL1_FINIT_BIT);
13881372
break;
13891373
}
13901374

@@ -1395,22 +1379,22 @@ static void dmic_stop(struct dai *dai)
13951379
for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
13961380
/* Don't stop CIC yet if both FIFOs were active */
13971381
if (dmic_active_fifos == 1) {
1398-
dmic_update_bits(dai, base[i] + CIC_CONTROL,
1399-
CIC_CONTROL_SOFT_RESET_BIT |
1400-
CIC_CONTROL_MIC_MUTE_BIT,
1401-
CIC_CONTROL_SOFT_RESET_BIT |
1402-
CIC_CONTROL_MIC_MUTE_BIT);
1382+
dai_update_bits(dai, base[i] + CIC_CONTROL,
1383+
CIC_CONTROL_SOFT_RESET_BIT |
1384+
CIC_CONTROL_MIC_MUTE_BIT,
1385+
CIC_CONTROL_SOFT_RESET_BIT |
1386+
CIC_CONTROL_MIC_MUTE_BIT);
14031387
}
14041388
switch (dai->index) {
14051389
case 0:
1406-
dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
1407-
FIR_CONTROL_A_MUTE_BIT,
1408-
FIR_CONTROL_A_MUTE_BIT);
1390+
dai_update_bits(dai, base[i] + FIR_CONTROL_A,
1391+
FIR_CONTROL_A_MUTE_BIT,
1392+
FIR_CONTROL_A_MUTE_BIT);
14091393
break;
14101394
case 1:
1411-
dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
1412-
FIR_CONTROL_B_MUTE_BIT,
1413-
FIR_CONTROL_B_MUTE_BIT);
1395+
dai_update_bits(dai, base[i] + FIR_CONTROL_B,
1396+
FIR_CONTROL_B_MUTE_BIT,
1397+
FIR_CONTROL_B_MUTE_BIT);
14141398
break;
14151399
}
14161400
}
@@ -1493,8 +1477,8 @@ static void dmic_irq_handler(void *data)
14931477
uint32_t val1;
14941478

14951479
/* Trace OUTSTAT0 register */
1496-
val0 = dmic_read(dai, OUTSTAT0);
1497-
val1 = dmic_read(dai, OUTSTAT1);
1480+
val0 = dai_read(dai, OUTSTAT0);
1481+
val1 = dai_read(dai, OUTSTAT1);
14981482
trace_dmic("dmic_irq_handler(), OUTSTAT0 = %u", val0);
14991483
trace_dmic("dmic_irq_handler(), OUTSTAT1 = %u", val1);
15001484

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