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37 workflow run results

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[pwm] add phase-correct PWM operation mode (#1445) Verilog Conversion #38: Commit afcde96 pushed by stnolting
7m 22s main
main
7m 22s
[pwm] add phase-correct PWM operation mode Verilog Conversion #37: Pull request #1445 synchronize by stnolting
7m 14s pwm_phase_correct
pwm_phase_correct
7m 14s
[docs] rework PWM section Verilog Conversion #36: Commit 0da851d pushed by stnolting
7m 43s pwm_phase_correct
pwm_phase_correct
7m 43s
[pwm] add phase-correct PWM operation mode Verilog Conversion #35: Pull request #1445 opened by stnolting
7m 11s pwm_phase_correct
pwm_phase_correct
7m 11s
[sw] update PWM HAL Verilog Conversion #34: Commit c534413 pushed by stnolting
7m 12s pwm_phase_correct
pwm_phase_correct
7m 12s
minor rtl edits and cleanups (#1444) Verilog Conversion #33: Commit 75452e8 pushed by stnolting
7m 10s main
main
7m 10s
minor rtl edits and cleanups Verilog Conversion #32: Pull request #1444 synchronize by stnolting
7m 17s dev061225
dev061225
7m 17s
minor rtl edits and cleanups Verilog Conversion #31: Pull request #1444 opened by stnolting
7m 12s dev061225
dev061225
7m 12s
[cache] minor edits Verilog Conversion #30: Commit d2943b0 pushed by stnolting
7m 19s dev061225
dev061225
7m 19s
[docs] minor cleanups Verilog Conversion #29: Commit 222bdca pushed by stnolting
7m 10s main
main
7m 10s
[readme] minor cleanups Verilog Conversion #28: Commit 60fa0ac pushed by stnolting
7m 14s main
main
7m 14s
[uart] remove sim-mode logging to file (#1443) Verilog Conversion #27: Commit 94a9452 pushed by stnolting
7m 9s main
main
7m 9s
[uart] remove sim-mode logging to file Verilog Conversion #26: Pull request #1443 synchronize by stnolting
7m 11s dev051225
dev051225
7m 11s
[tracer] minor assert note edits Verilog Conversion #25: Commit 0ac73c5 pushed by stnolting
7m 5s dev051225
dev051225
7m 5s
[uart] remove sim-mode logging to file Verilog Conversion #24: Pull request #1443 synchronize by stnolting
7m 14s dev051225
dev051225
7m 14s
[uart] remove sim-mode logging to file Verilog Conversion #23: Pull request #1443 opened by stnolting
7m 11s dev051225
dev051225
7m 11s
⚠️ [uart] remove sim-mode loggin to file Verilog Conversion #22: Commit a0d802e pushed by stnolting
7m 8s dev051225
dev051225
7m 8s
Move processor templates to neorv32-setups repository (#1442) Verilog Conversion #21: Commit 58ac037 pushed by stnolting
7m 0s main
main
7m 0s
Move processor templates to neorv32-setups repository Verilog Conversion #20: Pull request #1442 opened by stnolting
7m 5s relocate_templates
relocate_templates
7m 5s
[docs] update project folder overview Verilog Conversion #19: Commit 7b3182d pushed by stnolting
7m 25s relocate_templates
relocate_templates
7m 25s
fix minor OCD command-execution issue (#1440) Verilog Conversion #17: Commit ee716a5 pushed by stnolting
7m 10s main
main
7m 10s
fix minor OCD command-execution issue Verilog Conversion #16: Pull request #1440 synchronize by stnolting
7m 13s dev041225
dev041225
7m 13s
fix minor OCD command-execution issue Verilog Conversion #15: Pull request #1440 opened by stnolting
6m 46s dev041225
dev041225
6m 46s
[dm] stay in command busy state until halting again Verilog Conversion #14: Commit 0f75eb4 pushed by stnolting
7m 26s dev041225
dev041225
7m 26s
Add Verilog conversion flow (#1438) Verilog Conversion #13: Commit 9b6622f pushed by stnolting
7m 6s main
main
7m 6s