From 29386f3be40fa43ecc88c958d32a0dc2cf3d07d2 Mon Sep 17 00:00:00 2001 From: "xingyu.wu" Date: Fri, 31 Dec 2021 17:48:22 +0800 Subject: [PATCH] dts: starfive: Amend Vdec module device tree Add clock and reset nodes in Vdec module device tree. Signed-off-by: xingyu.wu --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) mode change 100644 => 100755 arch/riscv/boot/dts/starfive/jh7100.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi old mode 100644 new mode 100755 index 48f87141f00ee..fe8b911470cf0 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -407,8 +407,18 @@ vpu_dec: vpu_dec@118f0000 { compatible = "c&m,cm511-vpu"; reg = <0 0x118f0000 0 0x10000>; - clocks = <&clkgen JH7100_CLK_VP6_CORE>; - clock-names = "vcodec"; + clocks =<&clkgen JH7100_CLK_VDEC_AXI>, + <&clkgen JH7100_CLK_VDECBRG_MAIN>, + <&clkgen JH7100_CLK_VDEC_BCLK>, + <&clkgen JH7100_CLK_VDEC_CCLK>, + <&clkgen JH7100_CLK_VDEC_APB>; + clock-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; + resets = <&rstgen JH7100_RSTN_VDEC_AXI>, + <&rstgen JH7100_RSTN_VDECBRG_MAIN>, + <&rstgen JH7100_RSTN_VDEC_BCLK>, + <&rstgen JH7100_RSTN_VDEC_CCLK>, + <&rstgen JH7100_RSTN_VDEC_APB>; + reset-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; interrupts = <23>; //memory-region = <&vpu_reserved>; };