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DeepakRajendrakumaranDeepakRajendrakumaran
committed
Adding additional eGPR
1 parent 018b38e commit a91ef0b

9 files changed

Lines changed: 101 additions & 41 deletions

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‎src/coreclr/jit/compiler.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3188,7 +3188,7 @@ void Compiler::compInitOptions(JitFlags* jitFlags)
31883188
rbmAllInt |= RBM_HIGHINT;
31893189
rbmIntCalleeTrash |= RBM_HIGHINT;
31903190
cntCalleeTrashInt += CNT_CALLEE_TRASH_HIGHINT;
3191-
regIntLast = REG_R23;
3191+
regIntLast = REG_R31;
31923192
}
31933193
#endif // TARGET_AMD64
31943194

‎src/coreclr/jit/emit.h‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -752,8 +752,10 @@ class emitter
752752
// Note that we use the _idReg1 and _idReg2 fields to hold
753753
// the live gcrefReg mask for the call instructions on x86/x64
754754
//
755+
#if !defined(TARGET_AMD64)
755756
regNumber _idReg1 : REGNUM_BITS; // register num
756757
regNumber _idReg2 : REGNUM_BITS;
758+
#endif
757759

758760
////////////////////////////////////////////////////////////////////////
759761
// Space taken up to here:
@@ -776,6 +778,10 @@ class emitter
776778
unsigned _idCustom1 : 1;
777779
unsigned _idCustom2 : 1;
778780
unsigned _idCustom3 : 1;
781+
#if defined(TARGET_AMD64)
782+
regNumber _idReg1 : REGNUM_BITS; // register num
783+
regNumber _idReg2 : REGNUM_BITS;
784+
#endif
779785

780786
#define _idBound _idCustom1 /* jump target / frame offset bound */
781787
#define _idTlsGD _idCustom2 /* Used to store information related to TLS GD access on linux */
@@ -861,7 +867,7 @@ class emitter
861867
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
862868
#define ID_EXTRA_BITFIELD_BITS (14)
863869
#elif defined(TARGET_XARCH)
864-
#define ID_EXTRA_BITFIELD_BITS (17)
870+
#define ID_EXTRA_BITFIELD_BITS (19)
865871
#else
866872
#error Unsupported or unset target architecture
867873
#endif

‎src/coreclr/jit/emitxarch.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2475,7 +2475,7 @@ regNumber AbsRegNumber(regNumber reg)
24752475
bool IsExtendedReg(regNumber reg)
24762476
{
24772477
#ifdef TARGET_AMD64
2478-
return ((reg >= REG_R8) && (reg <= REG_R23)) || ((reg >= REG_XMM8) && (reg <= REG_XMM31));
2478+
return ((reg >= REG_R8) && (reg <= REG_R31)) || ((reg >= REG_XMM8) && (reg <= REG_XMM31));
24792479
#else
24802480
// X86 JIT operates in 32-bit mode and hence extended reg are not available.
24812481
return false;
@@ -5160,7 +5160,7 @@ inline UNATIVE_OFFSET emitter::emitInsSizeSV(instrDesc* id, code_t code, int var
51605160
static bool baseRegisterRequiresSibByte(regNumber base)
51615161
{
51625162
#ifdef TARGET_AMD64
5163-
return base == REG_ESP || base == REG_R12 || base == REG_R20;
5163+
return base == REG_ESP || base == REG_R12 || base == REG_R20 || base == REG_R28;
51645164
#else
51655165
return base == REG_ESP;
51665166
#endif
@@ -5169,7 +5169,7 @@ static bool baseRegisterRequiresSibByte(regNumber base)
51695169
static bool baseRegisterRequiresDisplacement(regNumber base)
51705170
{
51715171
#ifdef TARGET_AMD64
5172-
return base == REG_EBP || base == REG_R13 || base == REG_R21;
5172+
return base == REG_EBP || base == REG_R13 || base == REG_R21 || base == REG_R29;
51735173
#else
51745174
return base == REG_EBP;
51755175
#endif

‎src/coreclr/jit/emitxarch.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ inline static bool isHighGPReg(regNumber reg)
4343
#ifdef TARGET_AMD64
4444
// TODO-apx: the definition here is incorrect, we will need to revisit this after we extend the register definition.
4545
// for now, we can simply use REX2 as REX.
46-
return ((reg >= REG_R16) && (reg <= REG_R23));
46+
return ((reg >= REG_R16) && (reg <= REG_R31));
4747
#else
4848
// X86 JIT operates in 32-bit mode and hence extended regs are not available.
4949
return false;

‎src/coreclr/jit/lsra.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,8 @@ static const regMaskTP LsraLimitUpperSimdSet =
536536
(RBM_XMM16 | RBM_XMM17 | RBM_XMM18 | RBM_XMM19 | RBM_XMM20 | RBM_XMM21 | RBM_XMM22 | RBM_XMM23 | RBM_XMM24 |
537537
RBM_XMM25 | RBM_XMM26 | RBM_XMM27 | RBM_XMM28 | RBM_XMM29 | RBM_XMM30 | RBM_XMM31);
538538
static const regMaskTP LsraLimitExtGprSet =
539-
(RBM_R16 | RBM_R17 | RBM_R18 | RBM_R19 | RBM_R20 | RBM_R21 | RBM_R22 | RBM_R23 | RBM_ETW_FRAMED_EBP);
539+
(RBM_R16 | RBM_R17 | RBM_R18 | RBM_R19 | RBM_R20 | RBM_R21 | RBM_R22 | RBM_R23 | RBM_R24 | RBM_R25 | RBM_R26 |
540+
RBM_R27 | RBM_R28 | RBM_R29 | RBM_R30 | RBM_R31 | RBM_ETW_FRAMED_EBP);
540541
#elif defined(TARGET_ARM)
541542
// On ARM, we may need two registers to set up the target register for a virtual call, so we need
542543
// to have at least the maximum number of arg registers, plus 2.

‎src/coreclr/jit/register.h‎

Lines changed: 52 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -36,32 +36,41 @@ REGALIAS(RDI, EDI)
3636

3737
#else // !defined(TARGET_X86)
3838

39+
#define GPRMASK(x) (1ULL << (x))
3940
/*
4041
REGDEF(name, rnum, mask, sname) */
41-
REGDEF(RAX, 0, 0x00000001, "rax" )
42-
REGDEF(RCX, 1, 0x00000002, "rcx" )
43-
REGDEF(RDX, 2, 0x00000004, "rdx" )
44-
REGDEF(RBX, 3, 0x00000008, "rbx" )
45-
REGDEF(RSP, 4, 0x00000010, "rsp" )
46-
REGDEF(RBP, 5, 0x00000020, "rbp" )
47-
REGDEF(RSI, 6, 0x00000040, "rsi" )
48-
REGDEF(RDI, 7, 0x00000080, "rdi" )
49-
REGDEF(R8, 8, 0x00000100, "r8" )
50-
REGDEF(R9, 9, 0x00000200, "r9" )
51-
REGDEF(R10, 10, 0x00000400, "r10" )
52-
REGDEF(R11, 11, 0x00000800, "r11" )
53-
REGDEF(R12, 12, 0x00001000, "r12" )
54-
REGDEF(R13, 13, 0x00002000, "r13" )
55-
REGDEF(R14, 14, 0x00004000, "r14" )
56-
REGDEF(R15, 15, 0x00008000, "r15" )
57-
REGDEF(R16, 16, 0x00010000, "r16" )
58-
REGDEF(R17, 17, 0x00020000, "r17" )
59-
REGDEF(R18, 18, 0x00040000, "r18" )
60-
REGDEF(R19, 19, 0x00080000, "r19" )
61-
REGDEF(R20, 20, 0x00100000, "r20" )
62-
REGDEF(R21, 21, 0x00200000, "r21" )
63-
REGDEF(R22, 22, 0x00400000, "r22" )
64-
REGDEF(R23, 23, 0x00800000, "r23" )
42+
REGDEF(RAX, 0, GPRMASK(0), "rax" )
43+
REGDEF(RCX, 1, GPRMASK(1), "rcx" )
44+
REGDEF(RDX, 2, GPRMASK(2), "rdx" )
45+
REGDEF(RBX, 3, GPRMASK(3), "rbx" )
46+
REGDEF(RSP, 4, GPRMASK(4), "rsp" )
47+
REGDEF(RBP, 5, GPRMASK(5), "rbp" )
48+
REGDEF(RSI, 6, GPRMASK(6), "rsi" )
49+
REGDEF(RDI, 7, GPRMASK(7), "rdi" )
50+
REGDEF(R8, 8, GPRMASK(8), "r8" )
51+
REGDEF(R9, 9, GPRMASK(9), "r9" )
52+
REGDEF(R10, 10, GPRMASK(10), "r10" )
53+
REGDEF(R11, 11, GPRMASK(11), "r11" )
54+
REGDEF(R12, 12, GPRMASK(12), "r12" )
55+
REGDEF(R13, 13, GPRMASK(13), "r13" )
56+
REGDEF(R14, 14, GPRMASK(14), "r14" )
57+
REGDEF(R15, 15, GPRMASK(15), "r15" )
58+
REGDEF(R16, 16, GPRMASK(16), "r16" )
59+
REGDEF(R17, 17, GPRMASK(17), "r17" )
60+
REGDEF(R18, 18, GPRMASK(18), "r18" )
61+
REGDEF(R19, 19, GPRMASK(19), "r19" )
62+
REGDEF(R20, 20, GPRMASK(20), "r20" )
63+
REGDEF(R21, 21, GPRMASK(21), "r21" )
64+
REGDEF(R22, 22, GPRMASK(22), "r22" )
65+
REGDEF(R23, 23, GPRMASK(23), "r23" )
66+
REGDEF(R24, 24, GPRMASK(24), "r24" )
67+
REGDEF(R25, 25, GPRMASK(25), "r25" )
68+
REGDEF(R26, 26, GPRMASK(26), "r26" )
69+
REGDEF(R27, 27, GPRMASK(27), "r27" )
70+
REGDEF(R28, 28, GPRMASK(28), "r28" )
71+
REGDEF(R29, 29, GPRMASK(29), "r29" )
72+
REGDEF(R30, 30, GPRMASK(30), "r30" )
73+
REGDEF(R31, 31, GPRMASK(31), "r31" )
6574

6675
REGALIAS(EAX, RAX)
6776
REGALIAS(ECX, RCX)
@@ -75,11 +84,11 @@ REGALIAS(EDI, RDI)
7584
#endif // !defined(TARGET_X86)
7685

7786
#ifdef TARGET_AMD64
78-
#define XMMBASE 24
87+
#define XMMBASE 32
7988
#define XMMMASK(x) (1ULL << ((x)+XMMBASE))
8089

81-
#define KBASE 56
82-
#define KMASK(x) (1ULL << ((x)+KBASE))
90+
#define KBASE 64
91+
#define KMASK(x) (1ULL << ((x)))
8392

8493
#else // !TARGET_AMD64
8594
#define XMMBASE 8
@@ -224,6 +233,22 @@ REGDEF(STK, 8+KBASE, 0x0000, "STK" )
224233
#define REG_R22 JITREG_R22
225234
#undef REG_R23
226235
#define REG_R23 JITREG_R23
236+
#undef REG_R24
237+
#define REG_R24 JITREG_R24
238+
#undef REG_R25
239+
#define REG_R25 JITREG_R25
240+
#undef REG_R26
241+
#define REG_R26 JITREG_R26
242+
#undef REG_R27
243+
#define REG_R27 JITREG_R27
244+
#undef REG_R28
245+
#define REG_R28 JITREG_R28
246+
#undef REG_R29
247+
#define REG_R29 JITREG_R29
248+
#undef REG_R30
249+
#define REG_R30 JITREG_R30
250+
#undef REG_R31
251+
#define REG_R31 JITREG_R31
227252
#undef REG_EAX
228253
#define REG_EAX JITREG_EAX
229254
#undef REG_ECX

‎src/coreclr/jit/target.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,10 @@ typedef uint64_t regMaskSmall;
239239
#define HAS_MORE_THAN_64_REGISTERS 1
240240
#endif // TARGET_ARM64
241241

242+
#ifdef TARGET_AMD64
243+
#define HAS_MORE_THAN_64_REGISTERS 1
244+
#endif // TARGET_AMD64
245+
242246
#define REG_LOW_BASE 0
243247
#ifdef HAS_MORE_THAN_64_REGISTERS
244248
#define REG_HIGH_BASE 64

‎src/coreclr/jit/targetamd64.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@
102102
#define LAST_FP_ARGREG REG_XMM3
103103
#endif // !UNIX_AMD64_ABI
104104

105-
#define REGNUM_BITS 6 // number of bits in a REG_*
105+
#define REGNUM_BITS 7 // number of bits in a REG_*
106106
#define REGSIZE_BYTES 8 // number of bytes in one register
107107
#define XMM_REGSIZE_BYTES 16 // XMM register size in bytes
108108
#define YMM_REGSIZE_BYTES 32 // YMM register size in bytes
@@ -168,7 +168,7 @@
168168
#define REG_FLT_CALLEE_SAVED_LAST REG_XMM15
169169

170170
#define RBM_LOWINT RBM_ALLINT_INIT
171-
#define RBM_HIGHINT (RBM_R16|RBM_R17|RBM_R18|RBM_R19|RBM_R20|RBM_R21|RBM_R22|RBM_R23)
171+
#define RBM_HIGHINT (RBM_R16|RBM_R17|RBM_R18|RBM_R19|RBM_R20|RBM_R21|RBM_R22|RBM_R23|RBM_R24|RBM_R25|RBM_R26|RBM_R27|RBM_R28|RBM_R29|RBM_R30|RBM_R31)
172172

173173
#define RBM_ALLINT_INIT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH_INIT)
174174
#define RBM_ALLINT get_RBM_ALLINT()
@@ -265,7 +265,7 @@
265265
// when the hardware supports it. There are no additional hidden costs for these.
266266

267267
#ifdef UNIX_AMD64_ABI
268-
#define REG_VAR_ORDER_CALLEE_TRASH REG_EAX,REG_ECX,REG_EDX,REG_EDI,REG_ESI,REG_R8,REG_R9,REG_R10,REG_R11,REG_R16,REG_R17,REG_R18,REG_R19,REG_R20,REG_R21,REG_R22,REG_R23
268+
#define REG_VAR_ORDER_CALLEE_TRASH REG_EAX,REG_ECX,REG_EDX,REG_EDI,REG_ESI,REG_R8,REG_R9,REG_R10,REG_R11,REG_R16,REG_R17,REG_R18,REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28,REG_R29,REG_R30,REG_R31
269269
#define REG_VAR_ORDER_CALLEE_SAVED REG_EBX,REG_ETW_FRAMED_EBP_LIST REG_R15,REG_R14,REG_R13,REG_R12
270270

271271
#define REG_VAR_ORDER_FLT_CALLEE_TRASH REG_XMM0,REG_XMM1,REG_XMM2,REG_XMM3,REG_XMM4,REG_XMM5,REG_XMM6,REG_XMM7, \
@@ -279,7 +279,7 @@
279279
REG_XMM27,REG_XMM28,REG_XMM29,REG_XMM30,REG_XMM31
280280
#define REG_VAR_ORDER_FLT_EVEX_CALLEE_SAVED REG_VAR_ORDER_FLT_CALLEE_SAVED
281281
#else // !UNIX_AMD64_ABI
282-
#define REG_VAR_ORDER_CALLEE_TRASH REG_EAX,REG_ECX,REG_EDX,REG_R8,REG_R10,REG_R9,REG_R11,REG_R16,REG_R17,REG_R18,REG_R19,REG_R20,REG_R21,REG_R22,REG_R23
282+
#define REG_VAR_ORDER_CALLEE_TRASH REG_EAX,REG_ECX,REG_EDX,REG_R8,REG_R10,REG_R9,REG_R11,REG_R16,REG_R17,REG_R18,REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28,REG_R29,REG_R30,REG_R31
283283
#define REG_VAR_ORDER_CALLEE_SAVED REG_EBX,REG_ESI,REG_EDI,REG_ETW_FRAMED_EBP_LIST REG_R14,REG_R15,REG_R13,REG_R12
284284

285285
#define REG_VAR_ORDER_FLT_CALLEE_TRASH REG_XMM0,REG_XMM1,REG_XMM2,REG_XMM3,REG_XMM4,REG_XMM5
@@ -302,7 +302,7 @@
302302
#define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED)
303303

304304
#define CNT_CALLEE_TRASH_INT_INIT (9)
305-
#define CNT_CALLEE_TRASH_HIGHINT (8)
305+
#define CNT_CALLEE_TRASH_HIGHINT (16)
306306

307307
#define CNT_CALLEE_SAVED_FLOAT (0)
308308
#define CNT_CALLEE_TRASH_FLOAT_INIT (16)
@@ -315,7 +315,7 @@
315315
#define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED)
316316

317317
#define CNT_CALLEE_TRASH_INT_INIT (7)
318-
#define CNT_CALLEE_TRASH_HIGHINT (8)
318+
#define CNT_CALLEE_TRASH_HIGHINT (16)
319319

320320

321321
#define CNT_CALLEE_SAVED_FLOAT (10)
@@ -390,7 +390,7 @@
390390
// The following defines are useful for iterating a regNumber
391391
#define REG_FIRST REG_EAX
392392
#define REG_INT_FIRST REG_EAX
393-
#define REG_INT_LAST REG_R23
393+
#define REG_INT_LAST REG_R31
394394
#define REG_INT_COUNT (get_REG_INT_LAST() - REG_INT_FIRST + 1)
395395
#define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
396396
#define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))

‎src/coreclr/jit/unwindamd64.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,30 @@ short Compiler::mapRegNumToDwarfReg(regNumber reg)
9595
case REG_R23:
9696
dwarfReg = 23;
9797
break;
98+
case REG_R24:
99+
dwarfReg = 24;
100+
break;
101+
case REG_R25:
102+
dwarfReg = 25;
103+
break;
104+
case REG_R26:
105+
dwarfReg = 26;
106+
break;
107+
case REG_R27:
108+
dwarfReg = 27;
109+
break;
110+
case REG_R28:
111+
dwarfReg = 28;
112+
break;
113+
case REG_R29:
114+
dwarfReg = 29;
115+
break;
116+
case REG_R30:
117+
dwarfReg = 30;
118+
break;
119+
case REG_R31:
120+
dwarfReg = 31;
121+
break;
98122
default:
99123
noway_assert(!"unexpected REG_NUM");
100124
}

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