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SingleAccretionSingleAccretion
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Make intrinsic nodes multi op (aka delete GT_LIST) (#59912)
* Introducing GenTreeMultiOp * Rewrite gtNewSIMDNode * Rewrite gtNewSIMDVectorZero * Rewrite gtNewHWIntrinsicNode * Rewrite GenTreeSIMD::OperIsMemoryLoad * Rewrite GenTreeHWIntrinsic::OperIsMemoryLoad * Rewrite GenTreeHWIntrinsic::OperIsMemoryStore * Rewrite GenTree::IsIntegralConstVector * Rewrite GenTree::NullOp1Legal * Rewrite GenTree::IsSIMDZero * Rewrite GenTree::isCommutativeSIMDIntrinsic * Rewrite GenTree::isCommutativeHWIntrinsic * Rewrite GenTree::isContainableHWIntrinsic * Rewrite GenTree::isRMWHWIntrinsic * Rewrite GenTreeVisitor * Rewrite GenTreeUseEdgeIterator * Rewrite GenTree::VisitOperands * Rewrite GenTree::TryGetUse * Rewrite gtGetChildPointer * Rewrite gtHasRef * Rewrite fgSetTreeSeqHelper * Rewrite GenTree::NumChildren * Rewrite GenTree::GetChild * Rewrite GenTree::Compare * Rewrite gtCloneExpr * Rewrite gtSetEvalOrder * Rewrite gtHashValue * Rewrite gtDispTree * Rewrite fgDebugCheckFlags * Add genConsumeMultiOpOperands * Rewrite genConsumeRegs * Rewrite HWIntrinsic::HWIntrinsic * Rewrite HWIntrinsic::InitializeOperands * Delete HWIntrinsicInfo::lookupNumArgs * Delete HWIntrinsicInfo::lookupLastOp * Rewrite HWIntrinsicImmOpHelper ARM64 * Rewrite inst_RV_TT_IV * Rewrite inst_RV_RV_TT * Rewrite genSIMDIntrinsic XARCH * Rewrite genSIMDIntrinsicInit XARCH * Rewrite genSIMDIntrinsicInitN XARCH * Rewrite genSIMDIntrinsicUnOp XARCH * Rewrite genSIMDIntrinsic32BitConvert XARCH * Rewrite genSIMDIntrinsic64BitConvert XARCH * Rewrite genSIMDIntrinsicWiden XARCH * Rewrite genSIMDIntrinsicNarrow XARCH * Rewrite genSIMDIntrinsicBinOp XARCH * Rewrite genSIMDIntrinsicRelOp XARCH * Rewrite genSIMDIntrinsicShuffleSSE2 XARCH * Rewrite genSIMDIntrinsicUpperSave XARCH * Rewrite genSIMDIntrinsicUpperRestore XARCH * Rewrite genSIMDIntrinsic ARM64 * Rewrite genSIMDIntrinsicInit ARM64 * Rewrite genSIMDIntrinsicInitN ARM64 * Rewrite genSIMDIntrinsicUnOp ARM64 * Rewrite genSIMDIntrinsicWiden ARM64 * Rewrite genSIMDIntrinsicNarrow ARM64 * Rewrite genSIMDIntrinsicBinOp ARM64 * Rewrite genSIMDIntrinsicUpperSave ARM64 * Rewrite genSIMDIntrinsicUpperRestore ARM64 * Rewrite genHWIntrinsic_R_RM XARCH * Rewrite genHWIntrinsic_R_RM_I XARCH * Rewrite genHWIntrinsic_R_R_RM XARCH * Rewrite genHWIntrinsic_R_R_RM_I XARCH * Rewrite genHWIntrinsic_R_R_RM_R XARCH * Rewrite genHWIntrinsic_R_R_R_RM XARCH * Rewrite genHWIntrinsic XARCH * Rewrite genBaseIntrinsic XARCH * Rewrite genX86BaseIntrinsic XARCH * Rewrite genSSEIntrinsic XARCH * Rewrite genSSE2Intrinsic XARCH * Rewrite genSSE41Intrinsic XARCH * Rewrite genSSE42Intrinsic XARCH * Rewrite genAvxOrAvx2Intrinsic XARCH * Rewrite genBMI1OrBMI2Intrinsic XARCH * Rewrite genFMAIntrinsic XARCH * Rewrite genLZCNTIntrinsic XARCH * Rewrite genPOPCNTIntrinsic XARCH * Rewrite genXCNTIntrinsic XARCH * Rewrite genHWIntrinsic ARM64 * Rewrite insertUpperVectorSave * Rewrite insertUpperVectorRestore * Rewrite getKillSetForHWIntrinsic * Rewrite BuildSIMD XARCH * Rewrite BuildOperandUses/BuildDelayFreeUses * Rewrite BuildSIMD ARM64 * Rewrite BuildHWIntrinsic XARCH * Rewrite LowerSIMD XARCH * Rewrite ContainCheckSIMD XARCH * Rewrite LowerHWIntrinsicCC XARCH * Rewrite LowerFusedMultiplyAdd XARCH * Rewrite LowerHWIntrinsic XARCH * Rewrite LowerHWIntrinsicCmpOp XARCH * Rewrite LowerHWIntrinsicGetElement XARCH * Rewrite LowerHWIntrinsicWithElement XARCH * Rewrite LowerHWIntrinsicCreate XARCH * Rewrite LowerHWIntrinsicDot XARCH * Rewrite LowerHWIntrinsicToScalar XARCH * Rewrite IsContainableHWIntrinsicOp XARCH * Rewrite ContainCheckHWIntrinsic XARCH * Rewrite IsValidConstForMovImm ARM64 * Rewrite LowerHWIntrinsic ARM64 * Rewrite LowerHWIntrinsicFusedMultiplyAddScalar ARM64 * Rewrite LowerHWIntrinsicCmpOp ARM64 * Rewrite LowerHWIntrinsicCreate ARM64 * Rewrite LowerHWIntrinsicDot ARM64 * Rewrite ContainCheckStoreLoc ARM64 * Rewrite ContainCheckSIMD ARM64 * Rewrite ContainCheckHWIntrinsic ARM64 * Rewrite DecomposeHWIntrinsicGetElement X86 * Rewrite DecomposeHWIntrinsic X86 * Rewrite Rationalizer::RewriteNode * Rewrite optIsCSEcandidate * Rewrite fgValueNumberTree * Rewrite fgValueNumberSimd * Rewrite fgValueNumberHWIntrinsic * Rewrite GetVNFuncForNode * Rewrite fgMorphTree & fgMorphSmpOpOptional * Rewrite fgMorphFieldToSimdGetElement/fgMorphField * Rewrite fgMorphOneAsgBlockOp * Rewrite impInlineFetchArg * Rewrite impSIMDRelOp * Rewrite impSIMDIntrinsic * Rewrite impBaseIntrinsic XARCH * Rewrite impAvxOrAvx2Intrinsic XARCH * Rewrite impSpecialIntrinsic ARM64 * Fix SSA Builder comments * Delete GT_LIST * Support GTF_REVERSE_OPS for GenTreeMultiOp It turns out that in the time this change has been sitting there, 3 new methods in the SPMI benchmarks collection appeared, and it turns out they regress because of the lack of GTF_REVERSE_OPS. So, implement support for it.... This makes me quite sad, but it does make this change a pure zero-diff one, which is good. * Fix Linux x86 build break * Fix formatting * Improve readability through the use of a local * Support external operand arrays in GenTreeMultiOp * Fix formatting * Tweak a constructor call
1 parent ce93c29 commit 87b92fd

42 files changed

Lines changed: 2068 additions & 2483 deletions

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‎src/coreclr/jit/assertionprop.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1258,8 +1258,7 @@ AssertionIndex Compiler::optCreateAssertion(GenTree* op1,
12581258
optAssertionKind assertionKind,
12591259
bool helperCallArgs)
12601260
{
1261-
assert((op1 != nullptr) && !op1->OperIs(GT_LIST));
1262-
assert((op2 == nullptr) || !op2->OperIs(GT_LIST));
1261+
assert(op1 != nullptr);
12631262
assert(!helperCallArgs || (op2 != nullptr));
12641263

12651264
AssertionDsc assertion = {OAK_INVALID};

‎src/coreclr/jit/codegen.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1130,9 +1130,9 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
11301130

11311131
void genConsumeRegs(GenTree* tree);
11321132
void genConsumeOperands(GenTreeOp* tree);
1133-
#ifdef FEATURE_HW_INTRINSICS
1134-
void genConsumeHWIntrinsicOperands(GenTreeHWIntrinsic* tree);
1135-
#endif // FEATURE_HW_INTRINSICS
1133+
#if defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
1134+
void genConsumeMultiOpOperands(GenTreeMultiOp* tree);
1135+
#endif
11361136
void genEmitGSCookieCheck(bool pushReg);
11371137
void genCodeForShift(GenTree* tree);
11381138

‎src/coreclr/jit/codegenarm64.cpp‎

Lines changed: 37 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -3879,7 +3879,7 @@ void CodeGen::genSIMDIntrinsic(GenTreeSIMD* simdNode)
38793879
noway_assert(!"SIMD intrinsic with unsupported base type.");
38803880
}
38813881

3882-
switch (simdNode->gtSIMDIntrinsicID)
3882+
switch (simdNode->GetSIMDIntrinsicId())
38833883
{
38843884
case SIMDIntrinsicInit:
38853885
genSIMDIntrinsicInit(simdNode);
@@ -4039,15 +4039,15 @@ instruction CodeGen::getOpForSIMDIntrinsic(SIMDIntrinsicID intrinsicId, var_type
40394039
//
40404040
void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
40414041
{
4042-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicInit);
4042+
assert(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicInit);
40434043

4044-
GenTree* op1 = simdNode->gtGetOp1();
4044+
GenTree* op1 = simdNode->Op(1);
40454045
var_types baseType = simdNode->GetSimdBaseType();
40464046
regNumber targetReg = simdNode->GetRegNum();
40474047
assert(targetReg != REG_NA);
40484048
var_types targetType = simdNode->TypeGet();
40494049

4050-
genConsumeOperands(simdNode);
4050+
genConsumeMultiOpOperands(simdNode);
40514051
regNumber op1Reg = op1->IsIntegralConst(0) ? REG_ZR : op1->GetRegNum();
40524052

40534053
// TODO-ARM64-CQ Add LD1R to allow SIMDIntrinsicInit from contained memory
@@ -4090,16 +4090,18 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
40904090
//
40914091
void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
40924092
{
4093-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicInitN);
4093+
assert(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicInitN);
40944094

40954095
regNumber targetReg = simdNode->GetRegNum();
40964096
assert(targetReg != REG_NA);
40974097

4098-
var_types targetType = simdNode->TypeGet();
4099-
4100-
var_types baseType = simdNode->GetSimdBaseType();
4098+
var_types targetType = simdNode->TypeGet();
4099+
var_types baseType = simdNode->GetSimdBaseType();
4100+
emitAttr baseTypeSize = emitTypeSize(baseType);
4101+
regNumber vectorReg = targetReg;
4102+
size_t initCount = simdNode->GetOperandCount();
41014103

4102-
regNumber vectorReg = targetReg;
4104+
assert((initCount * baseTypeSize) <= simdNode->GetSimdSize());
41034105

41044106
if (varTypeIsFloating(baseType))
41054107
{
@@ -4108,24 +4110,17 @@ void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
41084110
vectorReg = simdNode->GetSingleTempReg(RBM_ALLFLOAT);
41094111
}
41104112

4111-
emitAttr baseTypeSize = emitTypeSize(baseType);
4112-
41134113
// We will first consume the list items in execution (left to right) order,
41144114
// and record the registers.
41154115
regNumber operandRegs[FP_REGSIZE_BYTES];
4116-
unsigned initCount = 0;
4117-
for (GenTree* list = simdNode->gtGetOp1(); list != nullptr; list = list->gtGetOp2())
4116+
for (size_t i = 1; i <= initCount; i++)
41184117
{
4119-
assert(list->OperGet() == GT_LIST);
4120-
GenTree* listItem = list->gtGetOp1();
4121-
assert(listItem->TypeGet() == baseType);
4122-
assert(!listItem->isContained());
4123-
regNumber operandReg = genConsumeReg(listItem);
4124-
operandRegs[initCount] = operandReg;
4125-
initCount++;
4126-
}
4118+
GenTree* operand = simdNode->Op(i);
4119+
assert(operand->TypeIs(baseType));
4120+
assert(!operand->isContained());
41274121

4128-
assert((initCount * baseTypeSize) <= simdNode->GetSimdSize());
4122+
operandRegs[i - 1] = genConsumeReg(operand);
4123+
}
41294124

41304125
if (initCount * baseTypeSize < EA_16BYTE)
41314126
{
@@ -4164,25 +4159,25 @@ void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
41644159
//
41654160
void CodeGen::genSIMDIntrinsicUnOp(GenTreeSIMD* simdNode)
41664161
{
4167-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicCast ||
4168-
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicConvertToSingle ||
4169-
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicConvertToInt32 ||
4170-
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicConvertToDouble ||
4171-
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicConvertToInt64);
4162+
assert((simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicCast) ||
4163+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicConvertToSingle) ||
4164+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicConvertToInt32) ||
4165+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicConvertToDouble) ||
4166+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicConvertToInt64));
41724167

4173-
GenTree* op1 = simdNode->gtGetOp1();
4168+
GenTree* op1 = simdNode->Op(1);
41744169
var_types baseType = simdNode->GetSimdBaseType();
41754170
regNumber targetReg = simdNode->GetRegNum();
41764171
assert(targetReg != REG_NA);
41774172
var_types targetType = simdNode->TypeGet();
41784173

4179-
genConsumeOperands(simdNode);
4174+
genConsumeMultiOpOperands(simdNode);
41804175
regNumber op1Reg = op1->GetRegNum();
41814176

41824177
assert(genIsValidFloatReg(op1Reg));
41834178
assert(genIsValidFloatReg(targetReg));
41844179

4185-
instruction ins = getOpForSIMDIntrinsic(simdNode->gtSIMDIntrinsicID, baseType);
4180+
instruction ins = getOpForSIMDIntrinsic(simdNode->GetSIMDIntrinsicId(), baseType);
41864181
emitAttr attr = (simdNode->GetSimdSize() > 8) ? EA_16BYTE : EA_8BYTE;
41874182

41884183
if (GetEmitter()->IsMovInstruction(ins))
@@ -4208,17 +4203,19 @@ void CodeGen::genSIMDIntrinsicUnOp(GenTreeSIMD* simdNode)
42084203
//
42094204
void CodeGen::genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode)
42104205
{
4211-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicSub || simdNode->gtSIMDIntrinsicID == SIMDIntrinsicBitwiseAnd ||
4212-
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicBitwiseOr || simdNode->gtSIMDIntrinsicID == SIMDIntrinsicEqual);
4206+
assert((simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicSub) ||
4207+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicBitwiseAnd) ||
4208+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicBitwiseOr) ||
4209+
(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicEqual));
42134210

4214-
GenTree* op1 = simdNode->gtGetOp1();
4215-
GenTree* op2 = simdNode->gtGetOp2();
4211+
GenTree* op1 = simdNode->Op(1);
4212+
GenTree* op2 = simdNode->Op(2);
42164213
var_types baseType = simdNode->GetSimdBaseType();
42174214
regNumber targetReg = simdNode->GetRegNum();
42184215
assert(targetReg != REG_NA);
42194216
var_types targetType = simdNode->TypeGet();
42204217

4221-
genConsumeOperands(simdNode);
4218+
genConsumeMultiOpOperands(simdNode);
42224219
regNumber op1Reg = op1->GetRegNum();
42234220
regNumber op2Reg = op2->GetRegNum();
42244221

@@ -4228,7 +4225,7 @@ void CodeGen::genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode)
42284225

42294226
// TODO-ARM64-CQ Contain integer constants where posible
42304227

4231-
instruction ins = getOpForSIMDIntrinsic(simdNode->gtSIMDIntrinsicID, baseType);
4228+
instruction ins = getOpForSIMDIntrinsic(simdNode->GetSIMDIntrinsicId(), baseType);
42324229
emitAttr attr = (simdNode->GetSimdSize() > 8) ? EA_16BYTE : EA_8BYTE;
42334230
insOpts opt = genGetSimdInsOpt(attr, baseType);
42344231

@@ -4257,9 +4254,9 @@ void CodeGen::genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode)
42574254
//
42584255
void CodeGen::genSIMDIntrinsicUpperSave(GenTreeSIMD* simdNode)
42594256
{
4260-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicUpperSave);
4257+
assert(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicUpperSave);
42614258

4262-
GenTree* op1 = simdNode->gtGetOp1();
4259+
GenTree* op1 = simdNode->Op(1);
42634260
GenTreeLclVar* lclNode = op1->AsLclVar();
42644261
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNode);
42654262
assert(emitTypeSize(varDsc->GetRegisterType(lclNode)) == 16);
@@ -4307,9 +4304,9 @@ void CodeGen::genSIMDIntrinsicUpperSave(GenTreeSIMD* simdNode)
43074304
//
43084305
void CodeGen::genSIMDIntrinsicUpperRestore(GenTreeSIMD* simdNode)
43094306
{
4310-
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicUpperRestore);
4307+
assert(simdNode->GetSIMDIntrinsicId() == SIMDIntrinsicUpperRestore);
43114308

4312-
GenTree* op1 = simdNode->gtGetOp1();
4309+
GenTree* op1 = simdNode->Op(1);
43134310
assert(op1->IsLocal());
43144311
GenTreeLclVar* lclNode = op1->AsLclVar();
43154312
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNode);

‎src/coreclr/jit/codegenarmarch.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -390,7 +390,6 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
390390
// This is handled at the time we call genConsumeReg() on the GT_COPY
391391
break;
392392

393-
case GT_LIST:
394393
case GT_FIELD_LIST:
395394
// Should always be marked contained.
396395
assert(!"LIST, FIELD_LIST nodes should always be marked contained.");

‎src/coreclr/jit/codegencommon.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1228,7 +1228,8 @@ unsigned CodeGenInterface::InferStructOpSizeAlign(GenTree* op, unsigned* alignme
12281228
{
12291229
opSize = (unsigned)op2->AsIntCon()->gtIconVal;
12301230
GenTree* op1 = op->AsOp()->gtOp1;
1231-
assert(op1->OperGet() == GT_LIST);
1231+
// TODO-List-Cleanup: this looks like some really old dead code.
1232+
// assert(op1->OperGet() == GT_LIST);
12321233
GenTree* dstAddr = op1->AsOp()->gtOp1;
12331234
if (dstAddr->OperGet() == GT_ADDR)
12341235
{

‎src/coreclr/jit/codegenlinear.cpp‎

Lines changed: 17 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1623,14 +1623,18 @@ void CodeGen::genConsumeRegs(GenTree* tree)
16231623
else if (tree->OperIs(GT_HWINTRINSIC))
16241624
{
16251625
// Only load/store HW intrinsics can be contained (and the address may also be contained).
1626-
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(tree->AsHWIntrinsic()->gtHWIntrinsicId);
1626+
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(tree->AsHWIntrinsic()->GetHWIntrinsicId());
16271627
assert((category == HW_Category_MemoryLoad) || (category == HW_Category_MemoryStore));
1628-
int numArgs = HWIntrinsicInfo::lookupNumArgs(tree->AsHWIntrinsic());
1629-
genConsumeAddress(tree->gtGetOp1());
1628+
size_t numArgs = tree->AsHWIntrinsic()->GetOperandCount();
1629+
genConsumeAddress(tree->AsHWIntrinsic()->Op(1));
16301630
if (category == HW_Category_MemoryStore)
16311631
{
1632-
assert((numArgs == 2) && !tree->gtGetOp2()->isContained());
1633-
genConsumeReg(tree->gtGetOp2());
1632+
assert(numArgs == 2);
1633+
1634+
GenTree* op2 = tree->AsHWIntrinsic()->Op(2);
1635+
assert(op2->isContained());
1636+
1637+
genConsumeReg(op2);
16341638
}
16351639
else
16361640
{
@@ -1674,7 +1678,6 @@ void CodeGen::genConsumeRegs(GenTree* tree)
16741678
// Return Value:
16751679
// None.
16761680
//
1677-
16781681
void CodeGen::genConsumeOperands(GenTreeOp* tree)
16791682
{
16801683
GenTree* firstOp = tree->gtOp1;
@@ -1690,54 +1693,25 @@ void CodeGen::genConsumeOperands(GenTreeOp* tree)
16901693
}
16911694
}
16921695

1693-
#ifdef FEATURE_HW_INTRINSICS
1696+
#if defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
16941697
//------------------------------------------------------------------------
1695-
// genConsumeHWIntrinsicOperands: Do liveness update for the operands of a GT_HWINTRINSIC node
1698+
// genConsumeOperands: Do liveness update for the operands of a multi-operand node,
1699+
// currently GT_SIMD or GT_HWINTRINSIC
16961700
//
16971701
// Arguments:
1698-
// node - the GenTreeHWIntrinsic node whose operands will have their liveness updated.
1702+
// tree - the GenTreeMultiOp whose operands will have their liveness updated.
16991703
//
17001704
// Return Value:
17011705
// None.
17021706
//
1703-
1704-
void CodeGen::genConsumeHWIntrinsicOperands(GenTreeHWIntrinsic* node)
1707+
void CodeGen::genConsumeMultiOpOperands(GenTreeMultiOp* tree)
17051708
{
1706-
int numArgs = HWIntrinsicInfo::lookupNumArgs(node);
1707-
GenTree* op1 = node->gtGetOp1();
1708-
if (op1 == nullptr)
1709+
for (GenTree* operand : tree->Operands())
17091710
{
1710-
assert((numArgs == 0) && (node->gtGetOp2() == nullptr));
1711-
return;
1712-
}
1713-
if (op1->OperIs(GT_LIST))
1714-
{
1715-
int foundArgs = 0;
1716-
assert(node->gtGetOp2() == nullptr);
1717-
for (GenTreeArgList* list = op1->AsArgList(); list != nullptr; list = list->Rest())
1718-
{
1719-
GenTree* operand = list->Current();
1720-
genConsumeRegs(operand);
1721-
foundArgs++;
1722-
}
1723-
assert(foundArgs == numArgs);
1724-
}
1725-
else
1726-
{
1727-
genConsumeRegs(op1);
1728-
GenTree* op2 = node->gtGetOp2();
1729-
if (op2 != nullptr)
1730-
{
1731-
genConsumeRegs(op2);
1732-
assert(numArgs == 2);
1733-
}
1734-
else
1735-
{
1736-
assert(numArgs == 1);
1737-
}
1711+
genConsumeRegs(operand);
17381712
}
17391713
}
1740-
#endif // FEATURE_HW_INTRINSICS
1714+
#endif // defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
17411715

17421716
#if FEATURE_PUT_STRUCT_ARG_STK
17431717
//------------------------------------------------------------------------

‎src/coreclr/jit/codegenxarch.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1673,7 +1673,6 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
16731673
// This is handled at the time we call genConsumeReg() on the GT_COPY
16741674
break;
16751675

1676-
case GT_LIST:
16771676
case GT_FIELD_LIST:
16781677
// Should always be marked contained.
16791678
assert(!"LIST, FIELD_LIST nodes should always be marked contained.");

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