Ensure we lie about the type for TYP_SIMD32 bitwise ops when only AVX is supported

Author: tannergooding

src/coreclr/jit/gentree.cpp

@@ -19133,14 +19133,22 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps  op,
             {
                 assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
 
-                if (varTypeIsFloating(simdBaseType) || !compOpportunisticallyDependsOn(InstructionSet_AVX2))
+                if (varTypeIsFloating(simdBaseType))
                 {
                     intrinsic = NI_AVX_And;
                 }
-                else
+                else if (compOpportunisticallyDependsOn(InstructionSet_AVX2))
                 {
                     intrinsic = NI_AVX2_And;
                 }
+                else
+                {
+                    // Since this is a bitwise operation, we can still support it by lying
+                    // about the type and doing the operation using a supported instruction
+
+                    intrinsic       = NI_AVX_And;
+                    simdBaseJitType = CORINFO_TYPE_FLOAT;
+                }
             }
             else if (simdBaseType == TYP_FLOAT)
             {
@@ -19159,14 +19167,22 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps  op,
             {
                 assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
 
-                if (varTypeIsFloating(simdBaseType) || !compOpportunisticallyDependsOn(InstructionSet_AVX2))
+                if (varTypeIsFloating(simdBaseType))
                 {
                     intrinsic = NI_AVX_AndNot;
                 }
-                else
+                else if (compOpportunisticallyDependsOn(InstructionSet_AVX2))
                 {
                     intrinsic = NI_AVX2_AndNot;
                 }
+                else
+                {
+                    // Since this is a bitwise operation, we can still support it by lying
+                    // about the type and doing the operation using a supported instruction
+
+                    intrinsic       = NI_AVX_AndNot;
+                    simdBaseJitType = CORINFO_TYPE_FLOAT;
+                }
             }
             else if (simdBaseType == TYP_FLOAT)
             {
@@ -19337,14 +19353,22 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps  op,
             {
                 assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
 
-                if (varTypeIsFloating(simdBaseType) || !compOpportunisticallyDependsOn(InstructionSet_AVX2))
+                if (varTypeIsFloating(simdBaseType))
                 {
                     intrinsic = NI_AVX_Or;
                 }
-                else
+                else if (compOpportunisticallyDependsOn(InstructionSet_AVX2))
                 {
                     intrinsic = NI_AVX2_Or;
                 }
+                else
+                {
+                    // Since this is a bitwise operation, we can still support it by lying
+                    // about the type and doing the operation using a supported instruction
+
+                    intrinsic       = NI_AVX_Or;
+                    simdBaseJitType = CORINFO_TYPE_FLOAT;
+                }
             }
             else if (simdBaseType == TYP_FLOAT)
             {
@@ -19390,14 +19414,22 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps  op,
             {
                 assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
 
-                if (varTypeIsFloating(simdBaseType) || !compOpportunisticallyDependsOn(InstructionSet_AVX2))
+                if (varTypeIsFloating(simdBaseType))
                 {
                     intrinsic = NI_AVX_Xor;
                 }
-                else
+                else if (compOpportunisticallyDependsOn(InstructionSet_AVX2))
                 {
                     intrinsic = NI_AVX2_Xor;
                 }
+                else
+                {
+                    // Since this is a bitwise operation, we can still support it by lying
+                    // about the type and doing the operation using a supported instruction
+
+                    intrinsic       = NI_AVX_Xor;
+                    simdBaseJitType = CORINFO_TYPE_FLOAT;
+                }
             }
             else if (simdBaseType == TYP_FLOAT)
             {
@@ -20458,18 +20490,19 @@ GenTree* Compiler::gtNewSimdDotProdNode(var_types   type,
                                         bool        isSimdAsHWIntrinsic)
 {
     assert(IsBaselineSimdIsaSupportedDebugOnly());
+    assert(varTypeIsArithmetic(type));
 
-    assert(varTypeIsSIMD(type));
-    assert(getSIMDTypeForSize(simdSize) == type);
+    var_types simdType = getSIMDTypeForSize(simdSize);
+    assert(varTypeIsSIMD(simdType));
 
     assert(op1 != nullptr);
-    assert(op1->TypeGet() == type);
+    assert(op1->TypeGet() == simdType);
 
     assert(op2 != nullptr);
-    assert(op2->TypeGet() == type);
+    assert(op2->TypeGet() == simdType);
 
     var_types simdBaseType = JitType2PreciseVarType(simdBaseJitType);
-    assert(varTypeIsArithmetic(simdBaseType));
+    assert(genActualType(simdBaseType) == type);
 
     NamedIntrinsic intrinsic = NI_Illegal;
 
@@ -21061,11 +21094,7 @@ GenTree* Compiler::gtNewSimdUnOpNode(genTreeOps  op,
 
         case GT_NOT:
         {
-            if (simdSize == 32)
-            {
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
-                assert(varTypeIsFloating(simdBaseType) || compIsaSupportedDebugOnly(InstructionSet_AVX2));
-            }
+            assert((simdSize != 32) || compIsaSupportedDebugOnly(InstructionSet_AVX));
 
             intrinsic = (simdSize == 32) ? NI_Vector256_get_AllBitsSet : NI_Vector128_get_AllBitsSet;
             op2       = gtNewSimdHWIntrinsicNode(type, intrinsic, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);

src/coreclr/jit/hwintrinsicxarch.cpp

@@ -1214,10 +1214,14 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic        intrinsic,
         {
             assert(sig->numArgs == 2);
 
-            op2 = impSIMDPopStack(retType);
-            op1 = impSIMDPopStack(retType);
+            if ((simdSize != 32) || varTypeIsFloating(simdBaseType) || compExactlyDependsOn(InstructionSet_AVX2))
+            {
+                op2 = impSIMDPopStack(retType);
+                op1 = impSIMDPopStack(retType);
 
-            retNode = gtNewSimdMaxNode(retType, op1, op2, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
+                retNode =
+                    gtNewSimdMaxNode(retType, op1, op2, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
+            }
             break;
         }
 
@@ -1226,10 +1230,14 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic        intrinsic,
         {
             assert(sig->numArgs == 2);
 
-            op2 = impSIMDPopStack(retType);
-            op1 = impSIMDPopStack(retType);
+            if ((simdSize != 32) || varTypeIsFloating(simdBaseType) || compExactlyDependsOn(InstructionSet_AVX2))
+            {
+                op2 = impSIMDPopStack(retType);
+                op1 = impSIMDPopStack(retType);
 
-            retNode = gtNewSimdMinNode(retType, op1, op2, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
+                retNode =
+                    gtNewSimdMinNode(retType, op1, op2, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
+            }
             break;
         }