diff --git a/coreneuron/apps/main1.cpp b/coreneuron/apps/main1.cpp
index 21faf5499..0b9dd9ae5 100644
--- a/coreneuron/apps/main1.cpp
+++ b/coreneuron/apps/main1.cpp
@@ -127,10 +127,10 @@ char* prepare_args(int& argc, char**& argv, int use_mpi, const char* arg) {
 }
 
 int corenrn_embedded_run(int nthread, int have_gaps, int use_mpi, int use_fast_imem, const char* arg) {
-    corenrn_embedded = 1;
+    corenrn_embedded = true;
     corenrn_embedded_nthread = nthread;
-    coreneuron::nrn_have_gaps = have_gaps;
-    if (use_fast_imem) {
+    coreneuron::nrn_have_gaps = have_gaps != 0;
+    if (use_fast_imem != 0) {
         coreneuron::nrn_use_fast_imem = true;
     }
 
@@ -143,7 +143,7 @@ int corenrn_embedded_run(int nthread, int have_gaps, int use_mpi, int use_fast_i
     free(new_arg);
     delete[] argv;
 
-    return corenrn_embedded;
+    return corenrn_embedded ? 1 : 0;
 }
 }
 
@@ -249,23 +249,23 @@ void nrn_init_and_load_data(int argc,
     report_mem_usage("Before nrn_setup");
 
     // set if need to interleave cells
-    use_interleave_permute = corenrn_param.cell_interleave_permute;
+    interleave_permute_type = corenrn_param.cell_interleave_permute;
     cellorder_nwarp = corenrn_param.nwarp;
     use_solve_interleave = corenrn_param.cell_interleave_permute;
 
 #if LAYOUT == 1
     // permuting not allowed for AoS
-    use_interleave_permute = 0;
-    use_solve_interleave = 0;
+    interleave_permute_type = 0;
+    use_solve_interleave = false;
 #endif
 
-    if (corenrn_param.gpu && use_interleave_permute == 0) {
+    if (corenrn_param.gpu && interleave_permute_type == 0) {
         if (nrnmpi_myid == 0) {
             printf(
                 " WARNING : GPU execution requires --cell-permute type 1 or 2. Setting it to 1.\n");
         }
-        use_interleave_permute = 1;
-        use_solve_interleave = 1;
+        interleave_permute_type = 1;
+        use_solve_interleave = true;
     }
 
     // pass by flag so existing tests do not need a changed nrn_setup prototype.
diff --git a/coreneuron/gpu/nrn_acc_manager.cpp b/coreneuron/gpu/nrn_acc_manager.cpp
index 6c1259d65..84d4ea151 100644
--- a/coreneuron/gpu/nrn_acc_manager.cpp
+++ b/coreneuron/gpu/nrn_acc_manager.cpp
@@ -329,7 +329,7 @@ void setup_nrnthreads_on_device(NrnThread* threads, int nthreads) {
         }
 
         if (nt->_permute) {
-            if (use_interleave_permute == 1) {
+            if (interleave_permute_type == 1) {
                 /* todo: not necessary to setup pointers, just copy it */
                 InterleaveInfo* info = interleave_info + i;
                 InterleaveInfo* d_info = (InterleaveInfo*)acc_copyin(info, sizeof(InterleaveInfo));
@@ -347,7 +347,7 @@ void setup_nrnthreads_on_device(NrnThread* threads, int nthreads) {
                 d_ptr = (int*)acc_copyin(info->cellsize, sizeof(int) * nt->ncell);
                 acc_memcpy_to_device(&(d_info->cellsize), &d_ptr, sizeof(int*));
 
-            } else if (use_interleave_permute == 2) {
+            } else if (interleave_permute_type == 2) {
                 /* todo: not necessary to setup pointers, just copy it */
                 InterleaveInfo* info = interleave_info + i;
                 InterleaveInfo* d_info = (InterleaveInfo*)acc_copyin(info, sizeof(InterleaveInfo));
diff --git a/coreneuron/io/mk_mech.cpp b/coreneuron/io/mk_mech.cpp
index 20a1c3cbf..d4d3d3c9b 100644
--- a/coreneuron/io/mk_mech.cpp
+++ b/coreneuron/io/mk_mech.cpp
@@ -51,16 +51,16 @@ int nrn_nobanner_;
 // NB: this should go away
 extern const char* nrn_version(int);
 
-int nrn_need_byteswap;
+bool nrn_need_byteswap;
 // following copied (except for nrn_need_byteswap line) from NEURON ivocvect.cpp
 #define BYTEHEADER   \
     uint32_t _II__;  \
     char* _IN__;     \
     char _OUT__[16]; \
-    int BYTESWAP_FLAG = 0;
+    bool BYTESWAP_FLAG = false;
 #define BYTESWAP(_X__, _TYPE__)                                 \
     BYTESWAP_FLAG = nrn_need_byteswap;                          \
-    if (BYTESWAP_FLAG == 1) {                                   \
+    if (BYTESWAP_FLAG) {                                        \
         _IN__ = (char*)&(_X__);                                 \
         for (_II__ = 0; _II__ < sizeof(_TYPE__); _II__++) {     \
             _OUT__[_II__] = _IN__[sizeof(_TYPE__) - _II__ - 1]; \
@@ -111,10 +111,10 @@ void mk_mech(const char* datpath) {
         // binary info in files needs to be byteswapped.
         int32_t x;
         nrn_assert(fread(&x, sizeof(int32_t), 1, f) == 1);
-        nrn_need_byteswap = 0;
+        nrn_need_byteswap = false;
         if (x != 1) {
             BYTEHEADER;
-            nrn_need_byteswap = 1;
+            nrn_need_byteswap = true;
             BYTESWAP(x, int32_t);
             nrn_assert(x == 1);
         }
@@ -128,7 +128,7 @@ static void mk_mech() {
     if (already_called) {
         return;
     }
-    nrn_need_byteswap = 0;
+    nrn_need_byteswap = false;
     std::stringstream ss;
     nrn_assert(nrn2core_mkmech_info_);
     (*nrn2core_mkmech_info_)(ss);
diff --git a/coreneuron/io/nrn2core_direct.h b/coreneuron/io/nrn2core_direct.h
index 1657f9374..4be4ada11 100644
--- a/coreneuron/io/nrn2core_direct.h
+++ b/coreneuron/io/nrn2core_direct.h
@@ -7,7 +7,7 @@ extern "C" {
 // The callbacks into nrn/src/nrniv/nrnbbcore_write.cpp to get
 // data directly instead of via files.
 
-extern int corenrn_embedded;
+extern bool corenrn_embedded;
 extern int corenrn_embedded_nthread;
 
 extern void (*nrn2core_group_ids_)(int*);
diff --git a/coreneuron/io/nrn_checkpoint.cpp b/coreneuron/io/nrn_checkpoint.cpp
index 5c4b129b5..e6e5239f3 100644
--- a/coreneuron/io/nrn_checkpoint.cpp
+++ b/coreneuron/io/nrn_checkpoint.cpp
@@ -45,7 +45,7 @@ THE POSSIBILITY OF SUCH DAMAGE.
 
 namespace coreneuron {
 bool nrn_checkpoint_arg_exists;
-int _nrn_skip_initmodel;
+bool _nrn_skip_initmodel;
 }  // namespace coreneuron
 #define UseFileHandlerWrap 0
 
@@ -868,7 +868,7 @@ bool checkpoint_initialize() {
 
     // in case some nrn_init allocate data we need to do that but do not
     // want to call initmodel.
-    _nrn_skip_initmodel = 1;
+    _nrn_skip_initmodel = true;
     for (int i = 0; i < nrn_nthread; ++i) {  // should be parallel
         NrnThread& nt = nrn_threads[i];
         for (NrnThreadMembList* tml = nt.tml; tml; tml = tml->next) {
@@ -879,7 +879,7 @@ bool checkpoint_initialize() {
             }
         }
     }
-    _nrn_skip_initmodel = 0;
+    _nrn_skip_initmodel = false;
 
     // if PatternStim exists, needs initialization
     for (NrnThreadMembList* tml = nrn_threads[0].tml; tml; tml = tml->next) {
diff --git a/coreneuron/io/nrn_setup.cpp b/coreneuron/io/nrn_setup.cpp
index 33a2626af..d52295c35 100644
--- a/coreneuron/io/nrn_setup.cpp
+++ b/coreneuron/io/nrn_setup.cpp
@@ -56,7 +56,7 @@ THE POSSIBILITY OF SUCH DAMAGE.
 
 
 /// --> Coreneuron
-int corenrn_embedded;
+bool corenrn_embedded;
 int corenrn_embedded_nthread;
 
 void (*nrn2core_group_ids_)(int*);
@@ -291,14 +291,14 @@ static void store_phase_args(int ngroup,
                              FileHandler* file_reader,
                              const char* path,
                              const char* restore_path,
-                             int byte_swap) {
+                             bool byte_swap) {
     ngroup_w = ngroup;
     gidgroups_w = gidgroups;
     imult_w = imult;
     file_reader_w = file_reader;
     path_w = path;
     restore_path_w = restore_path;
-    byte_swap_w = (bool)byte_swap;
+    byte_swap_w = byte_swap;
 }
 
 /* read files.dat file and distribute cellgroups to all mpi ranks */
@@ -333,7 +333,7 @@ void nrn_read_filesdat(int& ngrp, int*& grp, int multiple, int*& imult, const ch
     // being backward compatible
     if (iNumFiles == -1) {
         nrn_assert(fscanf(fp, "%d\n", &iNumFiles) == 1);
-        nrn_have_gaps = 1;
+        nrn_have_gaps = true;
         if (nrnmpi_myid == 0) {
             printf("Model uses gap junctions\n");
         }
@@ -672,7 +672,7 @@ void nrn_setup_cleanup() {
 
 void nrn_setup(const char* filesdat,
                bool is_mapping_needed,
-               int byte_swap,
+               bool byte_swap,
                bool run_setup_cleanup,
                const char* datpath,
                const char* restore_path,
@@ -1189,7 +1189,7 @@ void delete_trajectory_requests(NrnThread& nt) {
 }
 
 void read_phase2(FileHandler& F, int imult, NrnThread& nt) {
-    bool direct = corenrn_embedded ? true : false;
+    bool direct = corenrn_embedded;
     if (!direct) {
         assert(!F.fail());  // actually should assert that it is open
     }
@@ -1497,7 +1497,7 @@ void read_phase2(FileHandler& F, int imult, NrnThread& nt) {
         }
     }
 
-    if (nrn_have_gaps == 1) {
+    if (nrn_have_gaps) {
         nrn_partrans::gap_thread_setup(nt);
     }
 
@@ -1581,7 +1581,7 @@ void read_phase2(FileHandler& F, int imult, NrnThread& nt) {
        vectors will be read and will need to be permuted as well in subsequent
        sections of this function.
     */
-    if (use_interleave_permute) {
+    if (interleave_permute_type) {
         nt._permute = interleave_order(nt.id, nt.ncell, nt.end, nt._v_parent_index);
     }
     if (nt._permute) {
@@ -1628,7 +1628,7 @@ for (int i=0; i < nt.end; ++i) {
         }
     }
 
-    if (nrn_have_gaps == 1 && use_interleave_permute) {
+    if (nrn_have_gaps && interleave_permute_type) {
         nrn_partrans::gap_indices_permute(nt);
     }
 
diff --git a/coreneuron/mpi/nrnmpi.cpp b/coreneuron/mpi/nrnmpi.cpp
index 2436e7909..dc0f26bd2 100644
--- a/coreneuron/mpi/nrnmpi.cpp
+++ b/coreneuron/mpi/nrnmpi.cpp
@@ -61,7 +61,7 @@ extern void nrnmpi_checkbufleak();
 static int nrnmpi_under_nrncontrol_;
 
 void nrnmpi_init(int nrnmpi_under_nrncontrol, int* pargc, char*** pargv) {
-    nrnmpi_use = 1;
+    nrnmpi_use = true;
     nrnmpi_under_nrncontrol_ = nrnmpi_under_nrncontrol;
     if (nrnmpi_under_nrncontrol_) {
 #if !ALWAYS_CALL_MPI_INIT
@@ -87,7 +87,7 @@ void nrnmpi_init(int nrnmpi_under_nrncontrol, int* pargc, char*** pargv) {
             b = true;
         }
         if (!b) {
-            nrnmpi_use = 0;
+            nrnmpi_use = false;
             nrnmpi_under_nrncontrol_ = 0;
             return;
         }
@@ -153,7 +153,7 @@ void nrnmpi_terminate() {
         if (nrnmpi_under_nrncontrol_) {
             MPI_Finalize();
         }
-        nrnmpi_use = 0;
+        nrnmpi_use = false;
 #if nrnmpidebugleak
         nrnmpi_checkbufleak();
 #endif
diff --git a/coreneuron/mpi/nrnmpi.h b/coreneuron/mpi/nrnmpi.h
index 57add3d6c..6d81d7895 100644
--- a/coreneuron/mpi/nrnmpi.h
+++ b/coreneuron/mpi/nrnmpi.h
@@ -56,7 +56,7 @@ typedef struct {
     double spiketime;
 } NRNMPI_Spike;
 
-extern int nrnmpi_use; /* NEURON does MPI init and terminate?*/
+extern bool nrnmpi_use; /* NEURON does MPI init and terminate?*/
 
 }  // namespace coreneuron
 #include "coreneuron/mpi/nrnmpidec.h"
diff --git a/coreneuron/mpi/nrnmpi_def_cinc.h b/coreneuron/mpi/nrnmpi_def_cinc.h
index d74d3a994..4ecc38547 100644
--- a/coreneuron/mpi/nrnmpi_def_cinc.h
+++ b/coreneuron/mpi/nrnmpi_def_cinc.h
@@ -27,7 +27,7 @@ THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 namespace coreneuron {
-int nrnmpi_use;
+bool nrnmpi_use;
 int nrnmpi_numprocs = 1; /* size */
 int nrnmpi_myid = 0;     /* rank */
 int nrnmpi_numprocs_world = 1;
diff --git a/coreneuron/network/multisend.cpp b/coreneuron/network/multisend.cpp
index b9d6db06b..ea2fb1341 100644
--- a/coreneuron/network/multisend.cpp
+++ b/coreneuron/network/multisend.cpp
@@ -42,8 +42,8 @@ of spikes sent is equal to the number of spikes sent.
 // which has the greatest amount of overlap between computation
 // and communication.
 namespace coreneuron {
-int use_multisend_;
-int use_phase2_;
+bool use_multisend_;
+bool use_phase2_;
 int n_multisend_interval = 2;
 
 #if NRN_MULTISEND
@@ -352,7 +352,7 @@ static int multisend_advance() {
 
 #if NRN_MULTISEND
 void nrn_multisend_advance() {
-    if (use_multisend_ == 1) {
+    if (use_multisend_) {
         multisend_advance();
 #if ENQUEUE == 2
         multisend_receive_buffer[current_rbuf]->enqueue();
@@ -373,7 +373,7 @@ void nrn_multisend_receive(NrnThread* nt) {
 #endif
 //	w1 = nrn_wtime();
 #if NRN_MULTISEND & 1
-    if (use_multisend_ == 1) {
+    if (use_multisend_) {
         nrn_multisend_advance();
 #if 0 && ENQUEUE == 2
     // want the overlap with computation, not conserve
@@ -437,7 +437,7 @@ void nrn_multisend_cleanup() {
 
 void nrn_multisend_setup() {
     nrn_multisend_cleanup();
-    if (use_multisend_ == 0) {
+    if (!use_multisend_) {
         return;
     }
     nrnmpi_multisend_comm();
diff --git a/coreneuron/network/multisend.hpp b/coreneuron/network/multisend.hpp
index cade5b2fe..788912f5d 100644
--- a/coreneuron/network/multisend.hpp
+++ b/coreneuron/network/multisend.hpp
@@ -3,9 +3,9 @@
 
 #include "coreneuron/mpi/nrnmpiuse.h"
 namespace coreneuron {
-extern int use_multisend_;
+extern bool use_multisend_;
 extern int n_multisend_interval;
-extern int use_phase2_;
+extern bool use_phase2_;
 
 class PreSyn;
 class NrnThread;
@@ -18,6 +18,6 @@ void nrn_multisend_init();
 void nrn_multisend_cleanup();
 void nrn_multisend_setup();
 
-void nrn_multisend_setup_targets(int use_phase2, int*& targets_phase1, int*& targets_phase2);
+void nrn_multisend_setup_targets(bool use_phase2, int*& targets_phase1, int*& targets_phase2);
 }  // namespace coreneuron
 #endif  // nrnmultisend_h
diff --git a/coreneuron/network/multisend_setup.cpp b/coreneuron/network/multisend_setup.cpp
index 7b7b44dff..24aaa7638 100644
--- a/coreneuron/network/multisend_setup.cpp
+++ b/coreneuron/network/multisend_setup.cpp
@@ -288,7 +288,7 @@ to not use any PreSyn information.
 static int setup_target_lists(int, int**);
 static void fill_multisend_lists(int, int, int*, int*&, int*&);
 
-void nrn_multisend_setup_targets(int use_phase2, int*& targets_phase1, int*& targets_phase2) {
+void nrn_multisend_setup_targets(bool use_phase2, int*& targets_phase1, int*& targets_phase2) {
     int* r;
     int sz = setup_target_lists(use_phase2, &r);
 
diff --git a/coreneuron/network/netcvode.cpp b/coreneuron/network/netcvode.cpp
index efa8ffde7..9b64f0526 100644
--- a/coreneuron/network/netcvode.cpp
+++ b/coreneuron/network/netcvode.cpp
@@ -55,7 +55,7 @@ typedef void (*ReceiveFunc)(Point_process*, double*, double);
 
 double NetCvode::eps_;
 NetCvode* net_cvode_instance;
-int cvode_active_;
+bool cvode_active_;
 
 /// Flag to use the bin queue
 bool nrn_use_bin_queue_ = 0;
diff --git a/coreneuron/network/partrans.cpp b/coreneuron/network/partrans.cpp
index bac9bc655..e00b1a127 100644
--- a/coreneuron/network/partrans.cpp
+++ b/coreneuron/network/partrans.cpp
@@ -9,7 +9,7 @@
 // assert that every HalfGap instance in the thread have been a
 // ParallelContext.target(&HalfGap.vpre, sid)
 namespace coreneuron {
-int nrn_have_gaps;
+bool nrn_have_gaps;
 
 using namespace nrn_partrans;
 
diff --git a/coreneuron/network/partrans.hpp b/coreneuron/network/partrans.hpp
index f087a519f..83033ba72 100644
--- a/coreneuron/network/partrans.hpp
+++ b/coreneuron/network/partrans.hpp
@@ -5,7 +5,7 @@
 namespace coreneuron {
 struct Memb_list;
 
-extern int nrn_have_gaps;
+extern bool nrn_have_gaps;
 extern void nrnmpi_v_transfer();
 extern void nrnthread_v_transfer(NrnThread*);
 
diff --git a/coreneuron/nrnconf.h b/coreneuron/nrnconf.h
index 5d12a8626..67796f55a 100644
--- a/coreneuron/nrnconf.h
+++ b/coreneuron/nrnconf.h
@@ -56,7 +56,7 @@ extern double celsius;
 extern double t, dt;
 extern int rev_dt;
 extern int secondorder;
-extern int stoprun;
+extern bool stoprun;
 extern const char* bbcore_write_version;
 #define tstopbit (1 << 15)
 #define tstopset stoprun |= tstopbit
diff --git a/coreneuron/nrniv/nrniv_decl.h b/coreneuron/nrniv/nrniv_decl.h
index 4490dfb67..705991aa4 100644
--- a/coreneuron/nrniv/nrniv_decl.h
+++ b/coreneuron/nrniv/nrniv_decl.h
@@ -40,7 +40,7 @@ namespace coreneuron {
 /// mechanism types of Memb_list(>0) or time(0) passed from Neuron
 enum mech_type {voltage = -1, i_membrane_ = -2};
 
-extern int cvode_active_;
+extern bool cvode_active_;
 /// Vector of maps for negative presyns
 extern std::vector<std::map<int, PreSyn*> > neg_gid2out;
 /// Maps for ouput and input presyns
@@ -58,7 +58,7 @@ extern void mk_netcvode(void);
 extern void nrn_p_construct(void);
 extern void nrn_setup(const char* filesdat,
                       bool is_mapping_needed,
-                      int byte_swap,
+                      bool byte_swap,
                       bool run_setup_cleanup = true,
                       const char* datapath = "",
                       const char* restore_path = "",
@@ -75,7 +75,7 @@ extern void nrn_set_extra_thread0_vdata(void);
 extern Point_process* nrn_artcell_instantiate(const char* mechname);
 extern int nrnmpi_spike_compress(int nspike, bool gidcompress, int xchng);
 extern bool nrn_use_bin_queue_;
-extern int nrn_need_byteswap;
+extern bool nrn_need_byteswap;
 
 extern void nrn_outputevent(unsigned char, double);
 extern void ncs2nrn_integrate(double tstop);
@@ -90,7 +90,7 @@ extern double set_mindelay(double maxdelay);
 
 extern int nrn_soa_padded_size(int cnt, int layout);
 
-extern int use_interleave_permute;
+extern int interleave_permute_type;
 extern int cellorder_nwarp;
 }  // namespace coreneuron
 #endif
diff --git a/coreneuron/permute/cellorder.cpp b/coreneuron/permute/cellorder.cpp
index 2ae695d5a..74f997a5e 100644
--- a/coreneuron/permute/cellorder.cpp
+++ b/coreneuron/permute/cellorder.cpp
@@ -15,7 +15,7 @@
 #include <openacc.h>
 #endif
 namespace coreneuron {
-int use_interleave_permute;
+int interleave_permute_type;
 InterleaveInfo* interleave_info;  // nrn_nthread array
 
 
@@ -299,7 +299,7 @@ int* interleave_order(int ith, int ncell, int nnode, int* parent) {
         ii.firstnode = firstnode;
         ii.lastnode = lastnode;
         ii.cellsize = cellsize;
-        if (0 && ith == 0 && use_interleave_permute == 1) {
+        if (0 && ith == 0 && interleave_permute_type == 1) {
             printf("ith=%d nstride=%d ncell=%d nnode=%d\n", ith, nstride, ncell, nnode);
             for (int i = 0; i < ncell; ++i) {
                 printf("icell=%d cellsize=%d first=%d last=%d\n", i, cellsize[i], firstnode[i],
@@ -324,10 +324,10 @@ int* interleave_order(int ith, int ncell, int nnode, int* parent) {
             ii.cache_access = new size_t[nwarp];
             ii.child_race = new size_t[nwarp];
             for (int i = 0; i < nwarp; ++i) {
-                if (use_interleave_permute == 1) {
+                if (interleave_permute_type == 1) {
                     print_quality1(i, interleave_info[ith], ncell, p);
                 }
-                if (use_interleave_permute == 2) {
+                if (interleave_permute_type == 2) {
                     print_quality2(i, interleave_info[ith], p);
                 }
             }
@@ -661,7 +661,7 @@ void solve_interleaved1(int ith) {
 }
 
 void solve_interleaved(int ith) {
-    if (use_interleave_permute != 1) {
+    if (interleave_permute_type != 1) {
         solve_interleaved2(ith);
     } else {
         solve_interleaved1(ith);
diff --git a/coreneuron/permute/cellorder1.cpp b/coreneuron/permute/cellorder1.cpp
index dcf6a1c68..37fd2408f 100644
--- a/coreneuron/permute/cellorder1.cpp
+++ b/coreneuron/permute/cellorder1.cpp
@@ -8,7 +8,7 @@
 #include "coreneuron/permute/cellorder.hpp"
 #include "coreneuron/network/tnode.hpp"
 
-// just for use_interleave_permute
+// just for interleave_permute_type
 #include "coreneuron/nrniv/nrniv_decl.h"
 #include "coreneuron/utils/memory.h"
 
@@ -366,7 +366,7 @@ int* node_order(int ncell,
     level_from_root(nodevec);
 
     // nodevec[ncell:nnode] cells are interleaved in nodevec[0:ncell] cell order
-    if (use_interleave_permute == 1) {
+    if (interleave_permute_type == 1) {
         node_interleave_order(ncell, nodevec);
     } else {
         group_order2(nodevec, groupsize, ncell);
@@ -392,7 +392,7 @@ int* node_order(int ncell,
     }
 
     // administrative statistics for gauss elimination
-    if (use_interleave_permute == 1) {
+    if (interleave_permute_type == 1) {
         admin1(ncell, nodevec, nwarp, nstride, stride, firstnode, lastnode, cellsize);
     } else {
         //  admin2(ncell, nodevec, nwarp, nstride, stridedispl, stride, rootbegin, nodebegin,
diff --git a/coreneuron/sim/multicore.hpp b/coreneuron/sim/multicore.hpp
index e67d6360d..b47b8f487 100644
--- a/coreneuron/sim/multicore.hpp
+++ b/coreneuron/sim/multicore.hpp
@@ -37,7 +37,7 @@ namespace coreneuron {
 class NetCon;
 class PreSyn;
 
-extern int use_solve_interleave;
+extern bool use_solve_interleave;
 
 /*
    Point_process._presyn, used only if its NET_RECEIVE sends a net_event, is
@@ -171,7 +171,7 @@ extern void nrn_thread_table_check(void);
 
 extern void nrn_threads_free(void);
 
-extern int _nrn_skip_initmodel;
+extern bool _nrn_skip_initmodel;
 
 
 extern void dt2thread(double);
diff --git a/coreneuron/sim/solve_core.cpp b/coreneuron/sim/solve_core.cpp
index ffd2e1fcb..adaa5f3a3 100644
--- a/coreneuron/sim/solve_core.cpp
+++ b/coreneuron/sim/solve_core.cpp
@@ -30,7 +30,7 @@ THE POSSIBILITY OF SUCH DAMAGE.
 #include "coreneuron/permute/cellorder.hpp"
 #include "coreneuron/sim/multicore.hpp"
 namespace coreneuron {
-int use_solve_interleave;
+bool use_solve_interleave;
 
 static void triang(NrnThread*), bksub(NrnThread*);
 
diff --git a/coreneuron/utils/nrnoc_aux.cpp b/coreneuron/utils/nrnoc_aux.cpp
index 21efbdcc8..673429a5d 100644
--- a/coreneuron/utils/nrnoc_aux.cpp
+++ b/coreneuron/utils/nrnoc_aux.cpp
@@ -35,7 +35,7 @@ THE POSSIBILITY OF SUCH DAMAGE.
 #include "coreneuron/utils/nrnoc_aux.hpp"
 
 namespace coreneuron {
-int stoprun;
+bool stoprun;
 int v_structure_change;
 int diam_changed;
 #define MAXERRCOUNT 5
diff --git a/external/nmodl b/external/nmodl
index 58cb9409c..91c590514 160000
--- a/external/nmodl
+++ b/external/nmodl
@@ -1 +1 @@
-Subproject commit 58cb9409c5b4b0a2380ba5e1012903bbf2967266
+Subproject commit 91c5905146e9146f85e8d201fc9b2ed1e6bd6795