diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c
index c3652226a..23514bf89 100644
--- a/source/daplink/interface/swd_host.c
+++ b/source/daplink/interface/swd_host.c
@@ -3,7 +3,7 @@
  * @brief   Implementation of swd_host.h
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -27,6 +27,7 @@
 #include "debug_cm.h"
 #include "DAP_config.h"
 #include "DAP.h"
+#include "util.h"
 
 // Default NVIC and Core debug base addresses
 // TODO: Read these addresses from ROM.
@@ -115,8 +116,10 @@ uint8_t swd_init(void)
     return 1;
 }
 
+// This will turn off the related SWD GPIO and DAP where possible.
 uint8_t swd_off(void)
 {
+    swd_debug_deinit();
     PORT_OFF();
     return 1;
 }
@@ -773,6 +776,13 @@ static uint8_t JTAG2SWD()
     return 1;
 }
 
+// Sets reset active when asserted is 1. Returns always 1.
+uint8_t swd_set_target_reset(uint8_t asserted)
+{
+    (asserted) ? PIN_nRESET_OUT(0) : PIN_nRESET_OUT(1);
+    return 1;
+}
+
 uint8_t swd_init_debug(void)
 {
     uint32_t tmp = 0;
@@ -823,7 +833,7 @@ uint8_t swd_init_debug(void)
         return 0;
     }
 
-    // call a target dependant function:
+    // call a target dependent function:
     // some target can enter in a lock state
     // this function can unlock these targets
     target_unlock_sequence();
@@ -835,200 +845,209 @@ uint8_t swd_init_debug(void)
     return 1;
 }
 
-__attribute__((weak)) void swd_set_target_reset(uint8_t asserted)
+// This is target specific routine to disable DAP in order to conserve power.
+// Returns 1 on success, 0 otherwise.
+__attribute__((weak)) uint8_t swd_debug_deinit(void)
 {
-    (asserted) ? PIN_nRESET_OUT(0) : PIN_nRESET_OUT(1);
+    return 1;
 }
 
-uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state)
+// Some targets may require quirk before reset program (flashing).
+// Void pointer is used to pass type independent parameter (use casting).
+// Return 1 on success, 0 otherwise.
+__attribute__((weak)) uint8_t target_quirk_reset_pre_program(void *param)
 {
-    uint32_t val;
-    swd_init();
-
-    switch (state) {
-        case RESET_HOLD:
-            swd_set_target_reset(1);
-            break;
-
-        case RESET_RUN:
-            swd_set_target_reset(1);
-            os_dly_wait(2);
-            swd_set_target_reset(0);
-            os_dly_wait(2);
-            swd_off();
-            break;
-
-        case RESET_PROGRAM:
-            if (!swd_init_debug()) {
-                return 0;
-            }
-
-            // Enable debug
-            if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
-                return 0;
-            }
-
-            // Enable halt on reset
-            if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
-                return 0;
-            }
-
-            // Reset again
-            swd_set_target_reset(1);
-            os_dly_wait(2);
-            swd_set_target_reset(0);
-            os_dly_wait(2);
-
-            do {
-                if (!swd_read_word(DBG_HCSR, &val)) {
-                    return 0;
-                }
-            } while ((val & S_HALT) == 0);
-
-            // Disable halt on reset
-            if (!swd_write_word(DBG_EMCR, 0)) {
-                return 0;
-            }
-
-            break;
-
-        case NO_DEBUG:
-            if (!swd_write_word(DBG_HCSR, DBGKEY)) {
-                return 0;
-            }
-
-            break;
-
-        case DEBUG:
-            if (!JTAG2SWD()) {
-                return 0;
-            }
-
-            if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
-                return 0;
-            }
-
-            // Ensure CTRL/STAT register selected in DPBANKSEL
-            if (!swd_write_dp(DP_SELECT, 0)) {
-                return 0;
-            }
-
-            // Power up
-            if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
-                return 0;
-            }
-
-            // Enable debug
-            if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
-                return 0;
-            }
+    return 1;
+}
 
-            break;
+// ome targets may require quirk after reset program (flashing).
+// Void pointer is used to pass type independent parameter (use casting).
+// Return 1 on success, 0 otherwise.
+__attribute__((weak)) uint8_t target_quirk_reset_post_program(void *param)
+{
+    return 1;
+}
 
-        default:
-            return 0;
-    }
+// Some targets may require quirk before reset run.
+// Void pointer is used to pass type independent parameter (use casting).
+// Return 1 on success, 0 otherwise.
+__attribute__((weak)) uint8_t target_quirk_reset_pre_run(void *param)
+{
+    return 1;
+}
 
+// Some targets may require quirk after reset run.
+// Void pointer is used to pass type independent parameter (use casting).
+// Return 1 on success, 0 otherwise.
+__attribute__((weak)) uint8_t target_quirk_reset_post_run(void *param)
+{
     return 1;
 }
 
-uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state)
+/**
+ * Set Target State using SWJ access and/or hardware GPIO lines.
+ * Leverage switch(){} to construct multiple entry/exit pointq machine.
+ * First try Software Reset then Hardware Reset if the first fails.
+ * Parameters:
+ *  @param state is one of TARGET_RESET_STATE.
+ *  @returns 1 on success, 0 otherwise.
+ *  TODO: The same reset rework is necessary for Cortex-A SWD Host.
+ *  TODO: Functions prefixed target_ can be moved out to a separate
+ *   source code file and wrap swd_host{,_ca}.c routines.
+ */
+uint8_t target_set_state(TARGET_RESET_STATE state)
 {
-    uint32_t val;
+    uint32_t rsttype, ret;
     swd_init();
 
     switch (state) {
-        case RESET_HOLD:
-            swd_set_target_reset(1);
-            break;
-
+        case DEBUG:
         case RESET_RUN:
-            swd_set_target_reset(1);
-            os_dly_wait(2);
-            swd_set_target_reset(0);
-            os_dly_wait(2);
-            swd_off();
-            break;
-
+        case RESET_HOLD:
         case RESET_PROGRAM:
+            // Some Targeta may require pre reset quirks.
+            switch (state){
+                case DEBUG:
+                case RESET_HOLD:
+                case RESET_PROGRAM:
+                    if (!target_quirk_reset_pre_program(0)) return 0;
+                    break;
+            default:
+                if (!target_quirk_reset_pre_run(0)) return 0;
+                break;
+            }
+
+            // Initialize SWD DAP Port so we have a known state of the Target.
+            // DAP is essential for both software/hardware halt-on-reset.
             if (!swd_init_debug()) {
                 return 0;
             }
 
             // Enable debug and halt the core (DHCSR <- 0xA05F0003)
-            if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) {
-                return 0;
-            }
+            if (!target_debug_enable()) return 0;
+            if (!target_debug_halt()) return 0;
 
-            // Wait until core is halted
-            do {
-                if (!swd_read_word(DBG_HCSR, &val)) {
-                    return 0;
-                }
-            } while ((val & S_HALT) == 0);
+            // If we just want to enable debug we can return now.
+            if (state == DEBUG) return 1;
 
             // Enable halt on reset
-            if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
-                return 0;
+            if (!target_debug_halt_on_reset_enable()) return 0;
+
+            // Release possible hardware reset signal assertion that would keep
+            // core in reset state and so prevent software reset.
+            // Hardware reset may be asserted for security block operations.
+            target_reset_hw_assert(0);
+
+            // Try the available reset methods and then verify if core is halted.
+            for (rsttype=TARGET_RESET_SOFTWARE ; rsttype!=TARGET_RESET_NONE ; rsttype--)
+            {
+                if (rsttype == TARGET_RESET_HARDWARE) {
+                    ret = target_reset_hw();
+                } else if (rsttype == TARGET_RESET_SOFTWARE) {
+                    ret = target_reset_sw();
+                } else ret = 0;
+                if (ret == 0) break;
+                ret = target_debug_halt_check();
+                if (ret == 1) break;
             }
+            // Assert if reset-halt did not work (should not happen).
+            util_assert(ret);
 
-            // Perform a soft reset
-            if (!swd_write_word(NVIC_AIRCR, VECTKEY | SOFT_RESET)) {
-                return 0;
-            }
-
-            os_dly_wait(2);
-
-            do {
-                if (!swd_read_word(DBG_HCSR, &val)) {
-                    return 0;
-                }
-            } while ((val & S_HALT) == 0);
+            // Disable halt on reset whether we succeeded or not.
+            if (!target_debug_halt_on_reset_disable()) return 0;
 
-            // Disable halt on reset
-            if (!swd_write_word(DBG_EMCR, 0)) {
-                return 0;
+            // Target is now in RESET_HOLD / RESET_HOLD state.
+            // If this is the goal we may apply post halt quirk and return.
+            if (state==RESET_HOLD || state==RESET_PROGRAM) {
+                if (!target_quirk_reset_post_program(0)) return 0;
+                return ret;
             }
 
-            break;
+            // Continue from RESET_{HOLD,PROGRAM}.
+            // Now debug logic disable and run target.
+            for (int rsttype=TARGET_RESET_SOFTWARE ; rsttype!=TARGET_RESET_NONE ; rsttype--)
+            {
+                if (rsttype == TARGET_RESET_HARDWARE) {
+                    ret = target_reset_hw();
+                } else if (rsttype == TARGET_RESET_SOFTWARE) {
+                    ret = target_reset_sw();
+                } else ret = 0;
+                if (ret == 1) break;
+            }
+            util_assert(ret);
+            // NOTE: no break instruction here code will follow!
 
         case NO_DEBUG:
-            if (!swd_write_word(DBG_HCSR, DBGKEY)) {
-                return 0;
-            }
+            // Some Targets may require post reset run quirks.
+            if (!target_quirk_reset_post_run(0)) return 0;
+
+            // Make sure Target DAP is disabled to conserve power.
+            swd_off();
+            return ret;
 
+        default:
             break;
+    }
 
-        case DEBUG:
-            if (!JTAG2SWD()) {
-                return 0;
-            }
+    return 0;
 
-            if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
-                return 0;
-            }
+}
 
-            // Ensure CTRL/STAT register selected in DPBANKSEL
-            if (!swd_write_dp(DP_SELECT, 0)) {
-                return 0;
-            }
+static uint8_t target_debug_enable()
+{
+    // TODO: Consider using swd_enable_debug() here.
+    // Note: Debug enable may differ for Cortex-M and Cortex-A.
+    return swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN);
+}
 
-            // Power up
-            if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
-                return 0;
-            }
+static uint8_t target_debug_halt()
+{
+    return swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT);
+}
 
-            // Enable debug
-            if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
-                return 0;
-            }
+static uint8_t target_debug_halt_on_reset_enable()
+{
+    return swd_write_word(DBG_EMCR, VC_CORERESET);
+}
 
-            break;
+static uint8_t target_debug_halt_on_reset_disable()
+{
+    return swd_write_word(DBG_EMCR, 0);
+}
 
-        default:
+static uint8_t target_debug_halt_check()
+{
+    // TODO: Consider putting/using this code inside swd_host*.c common
+    // function swd_wait_until_halted() and call it here.
+    // Note that code will be different for Cortex-M and Cortex-A!
+    uint32_t val, timeout;
+    uint32_t time_start = os_time_get();
+    do {
+        if (!swd_read_word(DBG_HCSR, &val)) {
             return 0;
-    }
+        }
+        timeout = (os_time_get() - time_start) > TARGET_DELAY_RETRY;
+    } while ( (val & S_HALT)==0 && !timeout );
+    return !timeout;
+}
 
+static uint8_t target_reset_sw()
+{
+    return swd_write_word(NVIC_AIRCR, VECTKEY | SOFT_RESET);
+}
+
+static uint8_t target_reset_hw()
+{
+    target_reset_hw_assert(1);
+    os_dly_wait(TARGET_DELAY_RESET);
+    target_reset_hw_assert(0);
+    os_dly_wait(TARGET_DELAY_RESET);
     return 1;
 }
+
+static uint8_t target_reset_hw_assert(uint8_t asserted)
+{
+    return swd_set_target_reset(asserted);
+}
+
 #endif
diff --git a/source/daplink/interface/swd_host.h b/source/daplink/interface/swd_host.h
index 06337c3e0..5704256fa 100644
--- a/source/daplink/interface/swd_host.h
+++ b/source/daplink/interface/swd_host.h
@@ -37,6 +37,7 @@ extern "C" {
 uint8_t swd_init(void);
 uint8_t swd_off(void);
 uint8_t swd_init_debug(void);
+uint8_t swd_debug_deinit(void);
 uint8_t swd_read_dp(uint8_t adr, uint32_t *val);
 uint8_t swd_write_dp(uint8_t adr, uint32_t val);
 uint8_t swd_read_ap(uint32_t adr, uint32_t *val);
@@ -44,9 +45,21 @@ uint8_t swd_write_ap(uint32_t adr, uint32_t val);
 uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size);
 uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size);
 uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4);
-void swd_set_target_reset(uint8_t asserted);
-uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state);
-uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state);
+uint8_t swd_set_target_reset(uint8_t asserted);
+
+static uint8_t target_debug_enable(void);
+static uint8_t target_debug_halt(void);
+static uint8_t target_debug_halt_on_reset_enable(void);
+static uint8_t target_debug_halt_on_reset_disable(void);
+static uint8_t target_debug_halt_check(void);
+static uint8_t target_reset_sw(void);
+static uint8_t target_reset_hw(void);
+static uint8_t target_reset_hw_assert(uint8_t asserted);
+
+uint8_t target_quirk_reset_pre_program(void *param);
+uint8_t target_quirk_reset_post_program(void *param);
+uint8_t target_quirk_reset_pre_run(void *param);
+uint8_t target_quirk_reset_post_run(void *param);
 
 #ifdef __cplusplus
 }
diff --git a/source/daplink/interface/swd_host_ca.c b/source/daplink/interface/swd_host_ca.c
index 491b9a0b3..dd4acc72c 100644
--- a/source/daplink/interface/swd_host_ca.c
+++ b/source/daplink/interface/swd_host_ca.c
@@ -3,7 +3,7 @@
  * @brief   Implementation of swd_host.h
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -777,9 +777,10 @@ uint8_t swd_uninit_debug(void)
     return 1;
 }
 
-__attribute__((weak)) void swd_set_target_reset(uint8_t asserted)
+__attribute__((weak)) uint8_t swd_set_target_reset(uint8_t asserted)
 {
     (asserted) ? PIN_nRESET_OUT(0) : PIN_nRESET_OUT(1);
+    return 1;
 }
 
 uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state)
@@ -865,6 +866,7 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state)
     return 1;
 }
 
+// NOTE: This function does not work on Reneas R7S Cortex-A Target.
 uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state)
 {
     uint32_t val;
@@ -951,4 +953,17 @@ uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state)
     return 1;
 }
 
+// TODO: Align this code with Cortex-M when deidcated Target code is ready.
+uint8_t target_set_state(TARGET_RESET_STATE state)
+{
+    uint8_t res;
+    // This kind of fallback causes UMS flashing to fail on GR-PEACH!
+    // Reset works with HW/SW but RESET_HALT works only for HW.
+    //res = swd_set_target_state_sw(state);
+    //if (!res) {
+        res = swd_set_target_state_hw(state);
+    //}
+    return res;
+}
+
 #endif
diff --git a/source/hic_hal/target_config.h b/source/hic_hal/target_config.h
index ab6421dd6..2b82c75cc 100644
--- a/source/hic_hal/target_config.h
+++ b/source/hic_hal/target_config.h
@@ -40,6 +40,15 @@ extern "C" {
 // This can vary from target to target and should be in the structure or flash blob
 #define TARGET_AUTO_INCREMENT_PAGE_SIZE    (1024)
 
+/* TARGET RESET RELATED DEFINES */
+#define TARGET_DELAY_RESET  1       // How long do we wait after reset.
+#define TARGET_DELAY_RETRY  100     // How long do we wait with retries.
+enum TARGET_RESET_TYPES {           // Enumerate available reset types.
+    TARGET_RESET_NONE=0,            // No reset is also an option.
+    TARGET_RESET_HARDWARE=1,        // Hardware reset using GPIO.
+    TARGET_RESET_SOFTWARE=2         // Software reset using AIRCR.
+};
+
 /**
  @struct target_cfg_t
  @brief  The firmware configuration struct has unique about the chip its running on.
diff --git a/source/hic_hal/target_reset.h b/source/hic_hal/target_reset.h
index 439ccda47..388bc3c47 100644
--- a/source/hic_hal/target_reset.h
+++ b/source/hic_hal/target_reset.h
@@ -30,11 +30,11 @@ extern "C" {
 #endif
 
 typedef enum {
-    RESET_HOLD,              // Hold target in reset
+    RESET_HOLD,              // Hold target under reset asserted. TODO: Reset-Halt?
     RESET_PROGRAM,           // Reset target and setup for flash programming.
     RESET_RUN,               // Reset target and run normally
     NO_DEBUG,                // Disable debug on running target
-    DEBUG                    // Enable debug on running target
+    DEBUG,                   // Enable debug on running target
 } TARGET_RESET_STATE;
 
 void target_before_init_debug(void);
diff --git a/source/target/freescale/target_reset_Kseries.c b/source/target/freescale/target_reset_Kseries.c
index d1dca1dc6..f5d8653ad 100644
--- a/source/target/freescale/target_reset_Kseries.c
+++ b/source/target/freescale/target_reset_Kseries.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the Kinetis K series
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -30,7 +30,6 @@
 
 void target_before_init_debug(void)
 {
-    swd_set_target_reset(1);
 }
 
 void prerun_target_config(void)
@@ -55,6 +54,12 @@ void board_init(void)
 {
 }
 
+/**
+ * Unlock Sequence clears out the Security Bits and Flash Memory.
+ * NOTE: This leaves Hardware Reset line asserted on exit until halt!
+ * NOTE: During the unlock sequence the hardware reset must be asserted to
+ * ensure device code cannot execute / interfere with the unlocking procedure.
+ */
 uint8_t target_unlock_sequence(void)
 {
     uint32_t val;
@@ -150,7 +155,3 @@ uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
     return 0;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
diff --git a/source/target/freescale/target_reset_Lseries.c b/source/target/freescale/target_reset_Lseries.c
index aafa078e3..3075579bd 100644
--- a/source/target/freescale/target_reset_Lseries.c
+++ b/source/target/freescale/target_reset_Lseries.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the Kinetis L series
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -136,7 +136,3 @@ uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
     return 0;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
diff --git a/source/target/nordic/target_reset.c b/source/target/nordic/target_reset.c
index e07ffe57c..cec35ffee 100644
--- a/source/target/nordic/target_reset.c
+++ b/source/target/nordic/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the nrf51
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -38,12 +38,8 @@ uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
     return 0;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_sw(state);
-}
-
-void swd_set_target_reset(uint8_t asserted)
+// TODO: REMOVE THAT FUNCTION AFTER GLOBAL WAS INTRODUCED UNWEAK, VERIFY!
+void nrf_swd_set_target_reset(uint8_t asserted)
 {
     if (asserted) {
         swd_init_debug();
diff --git a/source/target/nordic/target_reset_nrf5x_sam3u2c.c b/source/target/nordic/target_reset_nrf5x_sam3u2c.c
index ebfedaeb8..2534a9b6e 100644
--- a/source/target/nordic/target_reset_nrf5x_sam3u2c.c
+++ b/source/target/nordic/target_reset_nrf5x_sam3u2c.c
@@ -24,27 +24,26 @@
 #include "DAP_config.h"
 #include "info.h"
 
+// For nRF chips CxxxPWRUPREQ is required, which is part of swd_init_debug().
 void target_before_init_debug(void)
 {
     return;
 }
 
+// TODO: Memory unlock routines can be added here for locked chips.
 uint8_t target_unlock_sequence(void)
 {
     return 1;
 }
 
+// TODO: Memory lock routines can be added here to lock the chip.
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_sw(state);
-}
-
-void swd_set_target_reset(uint8_t asserted)
+// TODO: Take the debug disable quirk from here..
+void nrf_swd_set_target_reset(uint8_t asserted)
 {
     const char *board_id;
     board_id = info_get_board_id();
diff --git a/source/target/nxp/lpc4088/target_reset.c b/source/target/nxp/lpc4088/target_reset.c
index 3df9b47e2..a650129ab 100644
--- a/source/target/nxp/lpc4088/target_reset.c
+++ b/source/target/nxp/lpc4088/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the lpc4088
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -59,22 +59,22 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
+uint8_t target_quirk_reset_pre_program(void *param)
 {
-    //return swd_set_target_state_hw(state);
-    uint8_t res;
-    if (state == RESET_PROGRAM)
-    {
-        gpio_set_isp_pin(0);
-        res = swd_set_target_state_hw(state);
-        gpio_set_isp_pin(1);
-    }
-    else
-    {
-        gpio_set_isp_pin(1);
-        res = swd_set_target_state_hw(state);
-    }
-    return res;
+    gpio_set_isp_pin(0);
+    return 1;
+}
+
+uint8_t target_quirk_reset_post_program(void *param)
+{
+    gpio_set_isp_pin(1);
+    return 1;
+}
+
+uint8_t target_quirk_reset_pre_run(void *param)
+{
+    gpio_set_isp_pin(1);
+    return 1;
 }
 
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
diff --git a/source/target/nxp/target_reset.c b/source/target/nxp/target_reset.c
index 86de9a1ad..c3db04df1 100644
--- a/source/target/nxp/target_reset.c
+++ b/source/target/nxp/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the lpc812
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -32,11 +32,6 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/onsemi/ncs36510/target_reset.c b/source/target/onsemi/ncs36510/target_reset.c
index 901e88043..d27c29ca1 100644
--- a/source/target/onsemi/ncs36510/target_reset.c
+++ b/source/target/onsemi/ncs36510/target_reset.c
@@ -1,5 +1,5 @@
 /* CMSIS-DAP Interface Firmware
- * Copyright (c) 2009-2013 ARM Limited
+ * Copyright (c) 2009-2017 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -27,11 +27,6 @@ uint8_t target_unlock_sequence(void) {
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state) {
-	/* sw reset preferred because hardware (pin) reset also resets debug logic */
-  return swd_set_target_state_sw(state); 
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size) {
     return 0;
 }
diff --git a/source/target/renesas/target_reset.c b/source/target/renesas/target_reset.c
index f40525b7d..eb3b6500f 100644
--- a/source/target/renesas/target_reset.c
+++ b/source/target/renesas/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the rza1h
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -32,11 +32,6 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/siliconlabs/target_reset.c b/source/target/siliconlabs/target_reset.c
index baed7c52c..f569c8c7c 100644
--- a/source/target/siliconlabs/target_reset.c
+++ b/source/target/siliconlabs/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the efm32gg
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -32,11 +32,6 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_sw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/st/nz32_sc151/target_reset.c b/source/target/st/nz32_sc151/target_reset.c
index c53c566ec..8068d1244 100644
--- a/source/target/st/nz32_sc151/target_reset.c
+++ b/source/target/st/nz32_sc151/target_reset.c
@@ -32,11 +32,6 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/st/target_reset.c b/source/target/st/target_reset.c
index 950f74951..e3dc97347 100644
--- a/source/target/st/target_reset.c
+++ b/source/target/st/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the stm32f407
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -37,7 +37,3 @@ uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
     return 0;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
diff --git a/source/target/st/xDot-L151/target_reset.c b/source/target/st/xDot-L151/target_reset.c
index 38c3478e8..8068d1244 100644
--- a/source/target/st/xDot-L151/target_reset.c
+++ b/source/target/st/xDot-L151/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the stm32l151
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -32,11 +32,6 @@ uint8_t target_unlock_sequence(void)
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state)
-{
-    return swd_set_target_state_hw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/toshiba/target_reset.c b/source/target/toshiba/target_reset.c
index de881ad1b..0fc38a7a9 100644
--- a/source/target/toshiba/target_reset.c
+++ b/source/target/toshiba/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the lpc812
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -23,10 +23,6 @@
 #include "target_reset.h"
 #include "swd_host.h"
 
-__attribute__((weak)) void target_set_state_by_board(TARGET_RESET_STATE state)
-{
-}
-
 void target_before_init_debug(void) {
     swd_set_target_reset(1);
     os_dly_wait(2);
@@ -39,11 +35,6 @@ uint8_t target_unlock_sequence(void) {
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state) {
-    target_set_state_by_board(state);
-    return swd_set_target_state_sw(state);
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;
diff --git a/source/target/wiznet/target_reset.c b/source/target/wiznet/target_reset.c
index 844c4fd56..8616b34e4 100644
--- a/source/target/wiznet/target_reset.c
+++ b/source/target/wiznet/target_reset.c
@@ -3,7 +3,7 @@
  * @brief   Target reset for the W7500 
  *
  * DAPLink Interface Firmware
- * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -23,23 +23,7 @@
 #include "target_reset.h"
 #include "swd_host.h"
 
-__attribute__((weak)) void target_set_state_by_board(TARGET_RESET_STATE state)
-{
-    if( state == RESET_PROGRAM )
-    {
-        do
-        {
-            swd_set_target_reset(1);
-            os_dly_wait(2);
-
-            swd_set_target_reset(0);
-            os_dly_wait(2);
-        } while(!swd_init_debug());
-    }
-}
-
 void target_before_init_debug(void) {
-    //swd_set_target_state_hw(RESET_HOLD);
     return;
 }
 
@@ -47,32 +31,6 @@ uint8_t target_unlock_sequence(void) {
     return 1;
 }
 
-uint8_t target_set_state(TARGET_RESET_STATE state) {
-    uint8_t status;
-    
-    target_set_state_by_board(state);
-    
-    if( state == RESET_RUN )
-    {
-        do
-        {
-            swd_set_target_reset(1);
-            os_dly_wait(2);
-            swd_set_target_reset(0);
-            os_dly_wait(2);
-        } while(!swd_init_debug());
-
-        swd_off();
-        status = 1;
-    }
-    else
-    {
-        status = swd_set_target_state_sw(state);
-    }
-    
-    return status;
-}
-
 uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
 {
     return 0;